Weeks 1-6:
- Set up development environment
- Refamiliarized myself with verilog
- Worked with team (Louai and Aaquil) on weekly assignments
- Primarily spent my own time working on the ALU while meeting up with team to discuss other assignments
- Began work on data memory test bench and tasked with working on control module
Up to 11/9:
- Link to repo: https://github.com/clavinator7/RISC-16-Processor-Project
- Finished control module and tested it
- Met with team to dicuss other completed modules (like instruction memory). We meet every week on Thursday
- Working on testing each module to ensure everything works together
- Starting the onboarding labs