Meeting 1 : Met with the team to define project scope and initialize the Git repository.Goals : Review RiSC-16 ISA specifications and establish the collaborative Verilog workflow.
Meeting 2 : Sync with Danish on Thursday at 1:00 PM.Work Completed :
Drafted logic for pc.v and instruction_memory.v following lecture architecture.
Note : Investigating a missing external dependency for the instruction memory module.
Meeting 3 : Consultation with Danish and Noahm regarding 16-bit processor partitioning.Work Completed :
Implemented data_memory.v and initial alu.v logic.
Clarified memory-mapped I/O versus standard data memory implementation.
Meeting 4 : Focused on core datapath integration and control logic.Work Completed :
Built the Register File (register_file.v) featuring eight 16-bit registers.
Developed the primary Control Module (control.v) to decode 3-bit opcodes.
Meeting 5 : Discussion on hardware verification and its role in industry.Work Completed :
Created a comprehensive ALU Testbench (alu_tb.v).
Performed functional simulations with a 1ns / 1ps timescale.
Work Completed :
Collaborated with Tony to refine the Register File for Assignment 3.
Optimized the internal MUX logic for MUXrf and MUXtgt.
Hardwired Register 0 to ground to ensure it remains a constant zero.
Work Completed :
Co-developed the Control Module logic to bridge the datapath sections.
Worked on the decoder to drive control signals based on the instruction opcode.
Pair-programmed to resolve persistent Verilog syntax and logic bugs.
Work Completed :
Conducted a full code review with Tony, focusing on the Register File and Control Module interfaces.
Synced module port names to ensure seamless integration into the top-level module.
Refined our shared understanding of hardware descriptive language best practices.
Spring Break : No project activity.
Work Completed :
Finalized the integration of all remaining RiSC-16 modules with Tony.
Verified the complete processor against test vectors.
Pushed the finalized codebase to the repository for the Sunday deadline.
Meeting : Discussed the transition from class assignments to the VIP final project.Work Completed :
Reviewed requirements for the final presentation.
Discussed the move toward specialized hardware: the Radar Systolic ASIC .
Work Completed :
Brainstormed implementation details for the systolic array accelerator.
Set up the project Discord and synchronized the GitHub repository environment.
Started drafting the technical documentation for the radar inference system.
Work Completed :
Integrated our individual work into the core project repository.
Co-authored the initial draft of the final presentation slides.
Verified the systolic array’s data flow logic with Tony.
Work Completed :
Finalized the presentation slide deck, focusing on our ASIC design and GitHub documentation.
Assigned delivery roles for the live presentation.
Updated the repository: radar-systolic-asic
Work Completed :
Delivered the final presentation to the VIP leads and peers.
Fielded questions regarding our systolic array architecture and submission requirements.
Discussion : The session was highly productive; seeing the other team projects provided great perspective. I’ve decided to continue with this VIP team next semester.