Hongtai’s Design Notebook

Week of September 8th

Project Work

  • Spent some time on reviewing the PowerPoint to confirm what to do this semester
  • Completed setup for github and created design notebook for this semester
  • Worked a few simple Verilog basics problem on the website in Powerpoint

Summary: this week is just beginning week. I plan to find a partner during next meeting. Also, I’d like to disscuss with team leader to continue work my project or restart the project this semester.

Week of September 14th

Project Work

  • Continued to do some Verilog practice questions on the HDLBits. I finished until “Declaring wires” problem.
  • Finished lab 1 this week. There are 3 more labs to be done.

Summary: This week I mainly discussed about what I continued to do next in the meeting with Darren. We plan to do on-boarding labs for a few weeks. Then we know how to test our code on board.

Week of September 21st

Project Work

  • Did 2 more Verilog practice questions on the HDLBits. I finished until “vector” problem.
  • Finished lab 2 this week. There are 2 more labs to be done.

Summary: I do not have much progess this week due to busy assignments and project of circuit. I will meet with team on Monday to talk about deadline of finishing all labs.

Week of September 28th

Project Work

  • Did 2 more Verilog practice questions on the HDLBits. I finished until “Four input gates” problem.
  • Finished lab 3 and almost half of lab 4 this week. There are 0.5 more labs to be done.

Summary: This week is less stressful than last week. I met with team and confirmed that we need to finish all labs this week. I will finish all 4 labs this week and then find meeting time with team for next step.

Week of October 5th

Project Work

  • Did more Verilog practice questions on the HDLBits. I finished until “Replication” problem.
  • Finished lab 4.

Summary: Now all labs are finished. For next week, I will find meeting time with team for next step.

Week of October 12th

Project Work

  • Did more Verilog practice questions on the HDLBits. I finished until “Connecting to poarts by position” problem.

Summary: This week I did not meet with team because I was busy with midterms and presentations. I did not have time to meet with team. I have one more midterm next week on Wednesday. I plan to meet with team on Friday or on weekend.

Week of October 19th

Project Work

  • Did more Verilog practice questions on the HDLBits. I finished until “Adder 1” problem.
  • Finished reading lab 5, even if it is incomplete.

Summary: I have one midterm and a presentation to prepare this week, so not a lot progress. Howver, this week I met with team and discussed the next step. I should work on the rest of the labs. Then I will assist other memebers in the future.

Week of October 26th

Project Work

  • Did more Verilog practice questions on the HDLBits. I finished until “Adder-substractor” problem.
  • Started testing some code of Lab 5 in VScode, but met some bugs. It seems due to the version of Verilog. Some code are not supported by the current version installed in my VScode.

Summary: This week I met with team on Wednesday, which is the weekly meeting in this semester. The team will work on Lab 1 and Lab 2 next week. I will prepare to assist on them. Also, due to the bug I met, I plan to debug it next week.

Week of November 2nd

Project Work

  • Did more Verilog practice questions on the HDLBits. I finished until “If statement” problem.
  • Figured out bugs I met on VScode. It is the problem with the command I typed in terminal. I need to add -g2012 to allow iVerilog know that it compiles with 2012 version of verilog. The new types, such as “logic” or “byte” cannot be recognized by the version of 2005. If I do not add -g2012 in the command, it compiles with version of 2005, which gives me a lot of errors in both testbench and design files.
  • I tested more codes until module TopLevel(). Mainly understand it because there is no exercise for it.

Summary: This week I spent most of the time on debugging the VScode. I plan to understand the rest of the code in lab 5 next week.

Week of November 9th

Project Work

  • Did more Verilog practice questions on the HDLBits. I finished until “Case statement” problem.
  • I tested more codes until title “Parameterized Modules & Interfaces”. I feel I am still confused by interface and modport. I understand the concepts in Verilog. Interfaces group related signals together and modports define directional views of those signals. I am still confused by how they worked together in Verilog. I think need some simple examples on illustrating them.

Summary: This week I spent most of the time testing the code and understanding concepts in lab 5. I will finish lab 5 next week. Also, I plan to finish lab 7 next week since I see lab 7 is mainly readings, not coding.

Week of November 16th

Project Work

  • Did more Verilog practice questions on the HDLBits. I finished until “Avoiding Latches” problem.
  • I finished lab 5. I read some documents of Verilog online and figured out meanings of “interface and modport”. I also like how the author of lab 5 explained parameters, such as the difference between “reg” and “logic”, which gives me deeper understanding of how Verilog works.
  • I also finsihed reading lab 7. It is about The RISC-V ISA specifications. I did not go deeper of that. It seems it is similar to ARM or x86. They are all instruction set architecture, but RISC-V is open-source. If I have time, I would like to know more about RISC-V ISA and maybe find a project to work on in the future.

Summary: I completed all current avaliable labs now. I talked to Darren and would like to challenge myself to finish RiSC-16 chip project on my own because I did program counter and register files last semester. Now, with more knowledge about Verilog, I could try finish other parts. If given time, I will try develop testbench code or ask leader for it.