Louai’s Design Notebook
My Group’s Project Repo: https://github.com/clavinator7/RISC-16-Processor-Project
Week of 22 September 2025 (Week 4)
Week 1 Catchup
Project Work:
- Completed “Design Notebooks and Git” and “Development Environment”
Had no issues following the instructions. Maybe a note should be added on the WSL section to make sure to update your version of Ubuntu to the latest version before attempting to add the new repos since that caused me a lot of headache.
Week of 13 October 2025 (Week 6)
Project Work:
- Completed pc.v and register_file.v
In the few weeks since the last update, I met with my group members Calvin and Aaquil several times to discuss the following:
- Calvin presents his implementation of alu.v and tasks for pc.v are delegated
- Louai presents his implementation of pc.v and tasks for register_file.v are delegated
- Louai helps Aaquil get caught up to speed on both implementations and Verilog basics
- register_file.v is started and some pair programming is done
- More work on register_file.v by me personally, Aaquil setting up his dev environment, and Calvin doing final tweaks on alu.v making sure all cases are passed, and merging the code into main.
Although we were not supposed to “delegate” modules and are supposed to work on them together, we meet after each module is completed to discuss every line of code and many questions are asked and answered. In the future, we will pair-program the more complex modules.
Week of 20 October 2025 (Week 7)
Project Work:
This week, I met with my group membeers Calvin and Aaquil to discuss my implementation of register_file.v. We also delegated the control module to Calvin, the program memory to Aaquil, and the data memory testbench to myself. It was concluded during the meeting that if Calvin finishes his module early, he can pick up any data mem tb work that I couldn’t finish.