Simon Hu - Design Notebook (Fall 2025)

Week 6

  • Learning data memory
  • Learning how to write testbench

Week 5 (Oct 6 - Oct 12)

  • Wrote Register file
  • Discussed and compared the register file with parnter
  • Tested Register file and passed all tests
  • All code uploaded (https://github.com/1fHu/ProcessorDesign.git)

Week 4

  • Wrote ALU model
  • Revised ALU test file and test my module
  • Passed all tests
  • Learning register file

Week 3

  • Revised Risc 16 Program Counter file
  • Added sign extention to immediate value before entering pc
  • Revised pc test file based on needed
  • Tested pc and passed all tests
  • Learning ALU model

Week 2 (Sep 15- Sep 21)

  • Read Risc 16 datasheet
  • Understood Program counter
  • Wrote code for p.c. of Risc 16
  • Compared the code with group partners
  • Uploaded the code to github repo (https://github.com/1fHu/ProcessorDesign/blob/main/pc16.v)
  • Finished HDLBits Vector

Week 1 (Sep 9–Sep 14)

  • Doing onboarding and finshed repo setup
  • finished HDLBits Getting Started and Verilog language basics