- Learning data memory
- Learning how to write testbench
- Wrote Register file
- Discussed and compared the register file with parnter
- Tested Register file and passed all tests
- All code uploaded (https://github.com/1fHu/ProcessorDesign.git)
- Wrote ALU model
- Revised ALU test file and test my module
- Passed all tests
- Learning register file
- Revised Risc 16 Program Counter file
- Added sign extention to immediate value before entering pc
- Revised pc test file based on needed
- Tested pc and passed all tests
- Learning ALU model
- Read Risc 16 datasheet
- Understood Program counter
- Wrote code for p.c. of Risc 16
- Compared the code with group partners
- Uploaded the code to github repo
(https://github.com/1fHu/ProcessorDesign/blob/main/pc16.v)
- Finished HDLBits Vector
- Doing onboarding and finshed repo setup
- finished HDLBits Getting Started and Verilog language basics