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Design Notebook: Processor Design VIP

Week 1: 01/20/26 - 01/25/26

  • Attended the first session of the VIP and introduced myself.
  • Got to know other members on the team.
  • My teammate Tyler and I decided to meet Thursdays at 1 PM.
  • Read through the resources on the VIP GitHub and the documentation section.

Discussion: Got introduced to Git and the Git workflow. Looking forward to settling into the team and understanding how everything is structured this semester.

Week 2: 01/26/26 - 02/01/26

  • Met with Tyler and Noah on Friday to go over Verilog concepts and clarify questions.
  • Tyler and I worked together on the Week 2 assignment.
  • Continued practicing Git commands and repository workflow.

Discussion: The meeting with Tyler and Noah was really helpful in clearing up confusion. Leraned more git push requests and branch management, and plan to keep practicing these workflows in the coming weeks.

Week 3: 02/02/26 - 02/08/26

  • Reviewed course materials and documentation shared by the team.
  • Continued building familiarity with Verilog concepts and the overall project structure.

Week 4: 02/09/26 - 02/15/26

  • Lightly skimmed through papers written by previous members to get context on the project.
  • Learned more Verilog in preparation for Assignment 2.
  • Completed Assignment 2 with Tyler.

Week 5: 02/16/26 - 02/22/26

  • Attended the VIP meeting from 6–7 PM on Wednesday.
  • Learned more about Git through a presentation given at the meeting.
  • Resolved an issue with my pull requests — with help from the team, I deleted my old branch and created a new branch containing all previous design notebooks.

Discussion: Finding out my pull requests were set up incorrectly was a good learning moment — cleaning it up by starting fresh with a properly structured branch was the move.

Week 6: 02/23/26 - 03/01/26

  • Began working on the Register File module for Assignment 3, configuring it to hold eight 16-bit registers for quick reference.
  • Implemented the logic to handle control inputs like MUXrf, WErf, and MUXtgt, while ensuring register 0 always safely maintains a value of zero.

Week 7: 03/02/26 - 03/07/26

  • Shifted focus to implementing the Control Module, which is responsible for tying each section of the processor together to ensure that it functions properly.
  • Developed the logic to accurately set all the wires and muxes to their correct values using only the 3-bit opcode from the instruction.
  • Debuged Verilog bugs.

Week 8: 03/07/26 - 03/13/26

  • Met with my teammate Tyler to review our Verilog code for the Register File and Control Module.
  • Debugged minor syntax issues and ensured all our module outputs aligned correctly.
  • Learned more verilog.

Week 9: 03/14/26 - 03/20/26 (Spring Break)

*updated design notebook

Week 10: 03/21/26 - 03/26/26

  • Finalized the remaining modules for the RiSC-16 processor.
  • Saved the final codebase to the repository and prepared the design notebook for Sunday’s submission.