Week of 29 January 2024
Project work:
- created the design notebook
This week, I mostly spent time wrapping my head aroud Github: froking, creating and understanding branches, commiting, pulling requests, pushing from lcoal machine to upstream
Week of 5 February 2024
Project work:
This week, I spent most of the time figuring out the error I got when I tried to push something from my local machine to my remote github repo but I had no luck so switched to Annubis just to get started with onbaording lab1. I downloaded VS Code with Git Lens extension, and I aim to work on it when working on my local computer. I plan on finishing lab1 by next week as well as successfully setting up the devlopment enviroment on my computer(mac).
Week of 12 February 2024
Project work:
This week, I spent trying to overcome the error I got when trying to push from my computer to github. I finally managed to overcome it by generating and using SSH key. I also finished lab 1 and familairized myself with the format of Makefiles and build systems
Week of 19 February 2024
Project work:
This week, I spent a lot of time revisitng verilog syntax and sequential and combinatorial concepts in Verilog. I also got introduced to the different test types and successfully completed lab 2.
Week of 26 February 2024
Project work:
This week, I started with lab 3 but encountered errors as I continued working on lab3. I then spent significant time setting up the development ennviroment on my laptop. I encounterted multiple errors when running cmake but was able to resolve it through installing the required packages I then spent most of the time trying to familaize myself with the testing frame and how to utilize it to configure appropriate tests for the given verilog modules and completed exercise 1 and 2.
Week of 4 March 2024
Project work:
This week, I spent alot of time trying to write the test code for exercise 3 but I had a lot going on because of midterm week so was not able to complete the entire lab. I was able to complete exercise 3 but at least one of my test fails. I hope to resolve this and complete lab 3 by next week as well as start on lab4
Week of 11 March 2024
Project work:
This week, I spent time completing lab 3 and could not do much else because I had couple of midterms this week
Week of 18 March 2024
Project work:
-None
Spring break
Week of 25 March 2024
Project work:
This week, I started with lab 4 but it took me long to progress through every step as I kept going back to reinforce what the different terminoligies referred to and what are their differences and their different uses: packages, tools and toolchains (which we learned earlier about), package manager, dependencies, registries
Week of 1 April 2024
Project work:
This week, I completed lab 4 and was able to gain a concrete understanding of the different things meant by libraries, packages, tools and toolchains, package manager, dependencies, registries, frameworks
After completing the verification section of the lab, I read a little more on design verification through this
Week of 8 April 2024
Project work:
-completed lab 5
This week, I completed lab 5 and got introduced to as well as gained a comprehsnive overview of the different Verilog data types and modules
Week of 15 April 2024
Project work:
-Read through lab 7
This week, I just went over the skills I gained during through the onboarding labs and familized myself with teh different teams in the Design Processor team which I can potentially contribute to. I could draw a lot of connections between the learned concepts in Comp Arch and the core team but before I actually contirbute to core, I wanted to research a little more on the CPU core so that I have a stronger conceptual undertstanding of what I would be contributing to as well as fill up some missing gaps from Comp Arch.
I read about:
Week of 22 April 2024
Project work:
-Worked on preparing final presentation & presented
This week, I spent time summarizing my work in the processor design team this semester in the form a presentation