Tony’s design notebook

week 1: 9/14-9/21

attended the online meeting
read rhrough the integer bas e of the RV32 ISA from the provided link
actually happened to take a class on the very same thing in grad comp arch, as the course focuses on RISC-V too

areas of interest:

out of the offered areas, im most interested in the bus / SoC work, particularly APB, AMBA, interrupt routing
would also be open to core stuff, especially something like the CSR / trap unit
I have verification experience, and have been working with formal verification tools in a reserarch lab for a while now - happy to jump no verification as well
- ive been meaning to learn UVM, as my experience is limited. if you think thats in scope, would love to get involved.
- i have access to a couple of FPGAs which i could use for emulation

read the excerpt on the architecture of a single cycle MIPS processor from Patterson and Hennessy
compared the MIPS implementation to what I know about the RV32 ISA

the control block is often the clock speed bottleneck, which is one of the central motivations for pipelining in processor design
sacrificing some space in the instruction is often worthwhile to make the placement of signal consistent or at least similar for many instructions
The ISA shapes the architecture - it is almost like a datapath spec
where possible, the decoding of instructions is hierarchical in a single-cycle MIPS processor, which helps simplify the control logic a lot