Yuhan Jiang’s Design Notebook
Week 1 — September 21, 2026
Work Completed
This week, I set up the development environment for the VIP project using WSL 2, Ubuntu, and VS Code. I installed Git and Verilator, configured GitHub SSH authentication, joined the NYU Processor Design organization, and forked and cloned the documentation repository. I also became familiar with the basic Git and pull request workflow for submitting weekly design notebook entries.
I briefly reviewed SystemVerilog and basic computer architecture concepts and began reading the RV32I documentation.
Project Interests
I am most interested in the Single-cycle Core team, particularly the Bus/SoC area. Since I am currently taking a SoC Design course, I would like to connect what I learn in class with this project. I am also interested in verification and learning how to test hardware designs.
I am also open to learning about other parts of the processor and helping with UART or SPI.
Week 2 — September 28, 2026
Work Completed
This week, I completed Lab 2 of the Processor Design VIP onboarding. I implemented and verified an 8-bit ALU, a parameterized counter, and a Moore FSM sequence detector using SystemVerilog and Verilator.
I also started reading Chapter 4, “The Processor,” from Patterson and Hennessy’s Computer Organization and Design for Group B.
What I Learned
From the reading, I developed a better understanding of the basic structure of a processor, including the program counter, instruction memory, register file, ALU, data memory, and control logic.
I also learned the difference between combinational logic and sequential logic, and how data moves through the processor during instruction execution.
The reading also helped me connect the concepts from Lab 2 to processor hardware, especially the use of combinational logic for the ALU and sequential logic for registers and state machines.