Ibrahim Hashim Design Notebook

Week 0 (Sep 15-21)

Attended the first team meeting
Reviewed SystemVerilog, went through my comparch notes
Skimmed the official RV32I documentation
I prefer to work on core because I want to gain a deeper understanding of processors, and I enjoy reasoning through datapaths, control signals, instruction execution, etc.

Note: Apologies for turning this in a day late, I thought that it was due tonight rather than last night. Noted for the future.

Attended the second team meeting
Looked through the given textbook Notes:
Datapaths are the components that store, move, and operate on values (registers, ALU, etc)
Control unit decodes the instruction and tells components what to do
Different instructions reuse much of the same hardware
Multiplexers make hardware sharing possible
The clock separates calculation from stored state
Control logic can be designed systematically (with a truth table)
One instruction per cycle does not necessarily mean a fast processor

Missed team meeting
Read through the email
Added an ADDI operand path detail to the Miro schematic and documented the reasoning in Module Abstractions.
Added sign extension from the 12 bit immediate to 32 bits and an operand mux that selects the immediate for the ALU.
Labeled the immediate, data, register address, and mux select connections with their bus widths.
Sign extension preserves negative constants, while the mux lets ADDI reuse the ALU’s ADD operation.

Attended team meeting
Reviewed the new project repository and the Git/GitHub workflow for working with my subteam
Reviewed the issue tracker and how module implementation and Level 1 verification are tracked separately.
Learned that Level 1 verification involves checking compilation and using SystemVerilog testbenches to generate waveforms and check basic correctness.
Preparing to work with my assigned sub-team on module implementation and Level 1 verification, due November 1.