Week 1 9/14-9/21
This week I attended weekly members meeting, got assigned into groups, and reviewed related concepts to prepare for group’s project. I also went over the RV32I documents and would like to be placed into UART + SPI group for further projects.
Week 2 9/21-9/28
Week 2 I attended the weekly meeting, went over the basics of Computer Architecture in the Patterson and Hennessy textbook. Reviewed the basic structure of a processor and how the datapath and control unit work together. The datapath is how the data moves and get operated on; the control executes the instruction and controls the datapath. This chapter also covers sequential and combinational logic. Combinational logic depends on the current inputs, while sequential stores value across clock cycles. The main concept is about single cycle processor design, in which each instruction should finish within one cycle.
Week 3 9/28-10/5
This week I read the module abstraction and contributed to the schema design by adding the diagram for R-type ALU instruction. I then added comments and reasoning behind my design choices in the shared google document.
Week 4 10/6-10/12
This week I attended the meeting and went over the schema with control signals table. I also reviewed what the other teammates have contributed to the schematic.
Week 5 10/13-10/18
Week 5 I joined the weekly meeting and updated my interest for module to implement in System Verilog. I will be in charge of the branch decoder section and will implement it in the following week.