Week 1
This week I completed the first Processor Design onboarding lab. I set up Git and Verilator, created a small SystemVerilog module and testbench, and practiced the branch and pull request workflow.
One difficulty I encountered was getting familiar with the Git workflow, especially understanding the difference between my fork, a branch, and the upstream repository. I learned that changes in my branch do not appear in the official repository until the pull request is merged.
Week 2
This week I completed the second Processor Design onboarding lab. I built an ALU, a counter, and a sequence detector in SystemVerilog. I learned how to use always_comb for combinational logic, always_ff for sequential logic, and states to build an FSM.
The main difficulty I had was udeveloping Moore and Mealy FSMs. In a Moore FSM, the output depends only on the current state, while in a Mealy FSM, it depends on both the current state and input. I realize that, for the sequence detector, a separate detection state is necessay to implement the required Moore FSM.