Week 1
This week I completed the first Processor Design onboarding lab. I set up Git and Verilator, created a small SystemVerilog module and testbench, and practiced the branch and pull request workflow.
One difficulty I encountered was getting familiar with the Git workflow, especially understanding the difference between my fork, a branch, and the upstream repository. I learned that changes in my branch do not appear in the official repository until the pull request is merged.
Week 2
This week I completed the second Processor Design onboarding lab. I built an ALU, a counter, and a sequence detector in SystemVerilog. I learned how to use always_comb for combinational logic, always_ff for sequential logic, and states to build an FSM.
The main difficulty I had was developing Moore and Mealy FSMs. In a Moore FSM, the output depends only on the current state, while in a Mealy FSM, it depends on both the current state and input. I realize that, for the sequence detector, a separate detection state is necessay to implement the required Moore FSM.
Week 3
This week I worked on Lab 3, which was about SystemVerilog verification and FIFO design. A lot of the material was new to me, so I spent a lot of time understanding the logic before I could write and test the code.
One of the biggest difficulties for me was understanding how the clock works in the testbench. At first, I was confused about when to change the inputs and when to check the outputs. I learned to change inputs around the negative edge of the clock, wait for the positive edge, and then check the result. Going through the tests one by one helped me understand this better.
The FIFO was also challenging because I had to understand the read and write pointers, the count, and the full and empty conditions. I tested different cases such as writing and reading data, filling and emptying the FIFO, pointer wraparound, and reading and writing at the same time.
Overall, this lab took me more time because many of these concepts were new to me, but working through the tests helped me understand the clock, testbenches, and FIFO logic better.
Week 4
This week, I reviewed the materials under the MICRO-ARCHITECTURE section, including module abstractions, RV32I specifications and implementation details, instruction documentation, and schema/control signal references.
Through this review, I gained a better understanding of the overall processor organization and how different hardware modules interact with each other. I learned how instruction decoding and control signals connect the datapath components and how the processor design is divided into smaller modules with specific responsibilities.
This review helped me build a clearer picture of the design flow and the role of each module before moving forward with implementation and integration. Understanding the relationship between the instruction set, control logic, and datapath will help me better approach future processor design tasks.