Week of 21 September 2026
Project Work:
- Processor Design Onboarding Repo: Completed Lab 1, including Verilator setup, SystemVerilog RTL/Testbench creation, and GitHub workflow.
This week I completed the first onboarding lab. The main focus was establishing a solid development environment and learning the Git/GitHub workflow required for the VIP. I wrote a 2-input AND gate in SystemVerilog along with its testbench, and simulated it successfully using Verilator.
The biggest hurdle I encountered was setting up the SSH keys and authenticating with GitHub in my WSL environment. I resolved it by manually starting the SSH agent, generating a new ed25519 key pair, and correctly mapping the public key to my GitHub account.
Week of 28 September 2026
Project Work:
- Processor Design Onboarding Repo: Completed Lab 2 (SystemVerilog RTL for an ALU, a synchronous counter, and a sequence detector).
This week I learned some of the core SystemVerilog fundamentals such as how to write synthesizable RTL using always_comb with blocking assignments for combinational logic, and always_ff with nonblocking assignments for sequential logic. The Moore FSM design for overlapping sequences helped to resolidified my understanding of state transitions.
Bugs/Issues Encountered:
While creating the alu.sv file in the WSL terminal, I somehow accidentally pasted the file creation command multiple times. This tangled the terminal’s input stream, leaving it stuck waiting for an end-of-file marker (showing a continuous > prompt).
Resolution: I resolved it by using managing to break out of the input loop, which restored my normal terminal prompt. I then cleanly overwrote the files one at a time. After that, the Verilator was able to be compiled and passed all testbenches perfectly!