Week of 21 September 2026
Project Work:
- Processor Design Onboarding Repo: Completed Lab 1, including Verilator setup, SystemVerilog RTL/Testbench creation, and GitHub workflow.
This week I completed the first onboarding lab. The main focus was establishing a solid development environment and learning the Git/GitHub workflow required for the VIP. I wrote a 2-input AND gate in SystemVerilog along with its testbench, and simulated it successfully using Verilator.
The biggest hurdle I encountered was setting up the SSH keys and authenticating with GitHub in my WSL environment. I resolved it by manually starting the SSH agent, generating a new ed25519 key pair, and correctly mapping the public key to my GitHub account.
Week of 28 September 2026
Project Work:
- Processor Design Onboarding Repo: Completed Lab 2 (SystemVerilog RTL for an ALU, a synchronous counter, and a sequence detector).
This week I learned some of the core SystemVerilog fundamentals such as how to write synthesizable RTL using always_comb with blocking assignments for combinational logic, and always_ff with nonblocking assignments for sequential logic. The Moore FSM design for overlapping sequences helped to resolidified my understanding of state transitions.
Bugs/Issues Encountered:
While creating the alu.sv file in the WSL terminal, I somehow accidentally pasted the file creation command multiple times. This tangled the terminal’s input stream, leaving it stuck waiting for an end-of-file marker (showing a continuous > prompt).
Resolution: I resolved it by using managing to break out of the input loop, which restored my normal terminal prompt. I then cleanly overwrote the files one at a time. After that, the Verilator was able to be compiled and passed all testbenches perfectly!
Week of 5 October 2026
Project Work:
- Processor Design Onboarding Repo: Completed Lab 3 (Verification, Reference Models, Accumulator testbench, and Parameterized Synchronous FIFO RTL + Testbench).
Tests Written:
For the 8-bit accumulator (accumulator_tb.sv), I wrote modular verification tasks (check_sum and apply_and_check) that drive inputs on the falling clock edge and verify outputs after the rising edge. My directed tests verified synchronous reset, single addition, multi-cycle accumulation, holding the sum for enable = 0, resuming accumulation when re-enabled, and 8-bit unsigned overflow wraparound, followed by 100 cycles of randomized testing against an expected_sum reference variable. For the synchronous FIFO (fifo_tb.sv), I wrote 10 directed test cases covering reset (empty = 1), single write/read round-trips, multi-value FIFO ordering, full assertion at DEPTH = 4, rejecting writes while full, draining to empty, rejecting reads while empty, pointer wraparound, and simultaneous accepted read/write, followed by 200 randomized cycles verified against a SystemVerilog dynamic queue (expected_queue[$]) with a #100us watchdog timer.
How the FIFO Works:
The parameterized fifo module (WIDTH = 8, DEPTH = 4) uses an unpacked memory array logic [WIDTH-1:0] mem [0:DEPTH-1], read and write pointers (rd_ptr and wr_ptr) that were sized to $clog2(DEPTH) bits that can wrap around at the end of the power of two memory, and an occupancy counter count that was sized to $clog2(DEPTH + 1) bits. Combinational logic sets empty = (count == 0) and full = (count == DEPTH), and determines accepted operations before the clock edge (do_write = wr_en && !full, do_read = rd_en && !empty). On each rising clock edge, an accepted write stores wr_data at mem[wr_ptr] and increments wr_ptr, an accepted read latches mem[rd_ptr] into rd_data and increments rd_ptr, and count increments on write only, decrements on read only, or remains unchanged when neither or both operations occur simultaneously.
Bugs and Edge Cases Encountered:
When compiling accumulator.sv and accumulator_tb.sv with Verilator, I initially hit a %Warning-TIMESCALEMOD compilation error because accumulator_tb.sv included `timescale 1ns/1ps while the accumulator.sv did not. Adding `timescale 1ns/1ps to the top of both of the RTL and the testbench files helped to fix the issue. I also made sure that do_write and do_read were evaluated using full and empty before the clock edge so that writes while full and reads while empty are rejected even if the opposite enable is asserted on the same cycle.
How Randomized Testing and the Reference Model Helped:
While directed tests verified the specific corner cases I manually planned for, combining $urandom_range stimulus with software style reference models (expected_sum for the accumulator and the dynamic queue expected_queue[$] using .push_back(), .pop_front(), and .size() for the FIFO) automatically verified hundreds of back to back read/write interleavings, repeated pointer wraparounds, and flag transitions without having to duplicate the RTL pointer hardware logic inside of the testbenches.
Week of 12 October 2026
Project Work & Mini Fall Break Updates: There was no formal design notebook assignment this week due to the mini fall break, so this entry summarizes our team’s recent architectural planning progress and our preparation for the upcoming module implementation phase.
Recent Discussion Recap: We briefly discussed computer architecture concepts and identified the core modules needed for the processor project and assigned a Miro board for collaborative schema design. We then developed an initial schema for the processor. To move forward, we divided the team into groups to begin module implementation, and we also merged Group A with Group B.
Microarchitecture Schema & Next Steps:
We will be reviewing the newly released microarchitecture schema (referencing the provided SCHEMA.jpg), as well as the documentation detailing team contributions, control signals, and specific instruction examples. The schematic outlines the main data path, including the Program Counter, Instruction Memory, Control Unit, Register File, ALU, and Data Memory, along with the instruction decoding for R, I, S, B, U, and J types. We will review many of these resources so we can continue after the small Fall Break.
Week of 12 October 2026
Project Work & Mini Fall Break Updates: There was no formal design notebook assignment this week due to the mini fall break, so this entry summarizes our team’s recent architectural planning progress and our preparation for the upcoming module implementation phase.
Recent Discussion Recap: We briefly discussed computer architecture concepts and identified the core modules needed for the processor project and assigned a Miro board for collaborative schema design. We then developed an initial schema for the processor. To move forward, we divided the team into groups to begin module implementation, and we also merged Group A with Group B.
Microarchitecture Schema & Next Steps:
We will be reviewing the newly released microarchitecture schema (referencing the provided SCHEMA.jpg), as well as the documentation detailing team contributions, control signals, and specific instruction examples. The schematic outlines the main data path, including the Program Counter, Instruction Memory, Control Unit, Register File, ALU, and Data Memory, along with the instruction decoding for R, I, S, B, U, and J types. We will review many of these resources so we can continue after the small Fall Break.