Week 1
This week I attended the first Processor Design meeting and completed lab 1 onboarding. I set up WSL, git and verilator this week and learned how to fork, pull and create repo’s on github as well.
Work
Week 2
This week I completed the onboarding lab 2. I brushed up on ALU and cmbinational and sequential logic through the exercises in the lab. I learned how to implement a MOORE FSM during this weeks lab as well. SOme issues that came I came across during this lab was some SM logic like not transitioning to the right state, but I was ablle to solve that relatively quickly by drawing out the MOORE model of the FSM.
Work
[Processor Design Onboarding Lab 2] https://github.com/JChen0916/processor-design-onboarding
Week 3
This week I completed onboarding Lab 3, where I learned how to build and verify a First-In, First-Out (FIFO) queue module in SystemVerilog. I gained hands-on experience structuring module hierarchy by composing larger digital designs from smaller functional modules. For the RTL design, I implemented a FIFO using a underlying memory array, read/write pointers, and occupancy tracking logic to handle status signals like full and empty.
A problem I came across was while building the verification environment. My first problem was a Verilator compile failure with 14 errors, all “can’t find definition” errors for the reference queue (expected_queue) and my statistics counters (n_writes, n_reads, and so on). The randomized-test tasks used these names, but they weren’t declared in a scope the tasks could see. I fixed this by declaring the queue and counters at module level, before the tasks that use them, so every task could access them.
Work
https://github.com/JChen0916/processor-design-onboarding/tree/main/lab_3
Week 4
This week I attended the weekly VIP meeting, where group A was officially merged onto group B. During the meeting, we went over the architecture schema and collaboratively drew out components based on the contributions team members added to the schema on MIRO.
Week 5
Attended weekly vip meeting discussed core modules implementations and sign ups. Will now be working on the data_mem.sv now that roles are finalized. For the next two weeks will now be working with the other people on data_mem.sv to implement and test it.