Darren’s Design Notebook
Week 0
This week I completed the first onboarding lab. I set up Verilator, created a small SystemVerilog module and testbench, and practiced the branch and pull request workflow. Also read about the official RV32I documentation and have a basic understanding of the processor we will be working on. I’m interested in working on Single-cycle Core and designing UART+SPI.
Work
Week 1
This week I completed lab2 and read the Patterson and Hennessy textbook. I learned that the register file can read and write to the same register in one clock cycle. This works because the old value is read first, and the new value is only saved at the clock edge. So, reading and writing at the same time will not mess up the data.