Darren’s Design Notebook
Week 0
This week I completed the first onboarding lab. I set up Verilator, created a small SystemVerilog module and testbench, and practiced the branch and pull request workflow. Also read about the official RV32I documentation and have a basic understanding of the processor we will be working on. I’m interested in working on Single-cycle Core and designing UART+SPI.
Work
Week 1
This week I completed lab2 and read the Patterson and Hennessy textbook. I learned that the register file can read and write to the same register in one clock cycle. This works because the old value is read first, and the new value is only saved at the clock edge. So, reading and writing at the same time will not mess up the data.
Work
Week 2
This week, I worked on the single-cycle RISC-V processor design. My main contribution was the “JALR” instruction path. JALR does two main things, which are PC = rs1 + immI and rd = old PC + 4.
The 12-bit immediate is sign-extended to 32 bits before going into the ALU. The ALU adds rs1 and the immediate to get the jump address. The lowest bit of the result is then forced to 0. I also added the PC + 4 writeback path so the return address can be stored in rd.
Week 3
This week, I attended our weekly meeting as usual. During the meeting, we worked together to finalize the microarchitecture schema, discussing the data paths for different instruction types and how they route through the corresponding registers and ALU inputs. We also reviewed how different instructions interact with the processor’s components.
Week 4
This week, I attended the team meeting and reviewed the new project repository and GitHub workflow for working with my subteam. I also reviewed the issue tracker and learned how module implementation and Level 1 verification are tracked separately. Level 1 verification involves checking compilation and using SystemVerilog testbenches to generate waveforms and check basic correctness. I was assigned to work on data_mem.sv, which handles combinational reads, sequential writes, different load/store sizes, and sign extension for loads. I will work with my subteam to complete the data memory implementation and Level 1 verification by November 1.