Xingyu’s Design Notebook
Week of 14 September 2026
Project Work
- First Design Notebook PR #560: Created my first design notebook and submitted a pull request.
This week, I set up my development environment by configuring Git, GitHub, and SSH authentication. I forked and cloned the official repository, created a working branch named xingyu-lab1, and added my first design notebook. I committed and pushed my changes to GitHub and opened PR #560.
During the setup, I initially entered the cd command incorrectly because I missed a space. I corrected the command and successfully navigated to the repository. I also verified that SSH authentication and Verilator were working correctly.
Lab 1: My First RTL Project
- My Onboarding Repository: Completed Lab 1.
I am not familiar with Git and SystemVerilog yet. For this lab, I mostly copied and pasted the example code from the lab manual. I created a simple AND gate and a testbench. I followed the instructions to use Verilator, and all four tests passed.
I learned some basic Git commands and how to run a simulation. I still don’t fully understand all the SystemVerilog code, especially the testbench. I also had some trouble using Terminal because I accidentally typed file names as commands. I hope to understand the code better in future labs.
Week of 27 September 2026
Lab 2: SystemVerilog RTL Fundamentals
This week, I completed Lab 2 and learned the basics of SystemVerilog RTL. I built an ALU using always_comb, a counter using always_ff, and a Moore FSM that detects 1011. I also learned the difference between blocking (=) and nonblocking (<=) assignments.
For most of this lab, I followed the lab instructions and copied and pasted much of the provided code, then modified the missing parts and ran the tests.
I had some trouble saving alu.sv in Pico because of an “Illegal byte sequence” error. I solved it by writing the file from Terminal using cat and EOF. I also had trouble understanding overlapping FSM transitions, but I learned that the FSM keeps partial matches instead of always returning to S0.
All ALU, counter, and sequence detector tests passed with Verilator.
Week of 5 October 2026
Lab 3: SystemVerilog Verification and FIFO Design
This week, I learned how to verify SystemVerilog designs using self-checking testbenches. I wrote directed and randomized tests for an accumulator and a FIFO.
For the FIFO, I tested reset, normal reads and writes, full and empty conditions, pointer wraparound, simultaneous read/write, and rejected operations when full or empty. The FIFO uses memory, read/write pointers, and a count to track how many entries are stored.
I also used randomized testing and a reference model. The reference queue kept track of the expected FIFO data, which made it easier to compare the DUT output with the correct result over many random cycles.
I had some trouble with Verilator width warnings and accidentally entered SystemVerilog code directly into the Terminal. I fixed the width issue by using a wider temporary random variable and then selecting the needed bits.
All accumulator and FIFO tests passed with Verilator.
Week of 12 October 2026
Processor Microarchitecture
This week, I looked at the processor schema and the Module Abstractions document. I am still new to computer architecture, so I focused on understanding the basic parts of the processor.
I learned that the register file stores values in registers, and the ALU is used to do operations such as addition and subtraction. I also learned that the processor uses different connections and control signals to decide where data should go. I am still not sure which module group I was assigned to after the groups were merged, so I have not started working on a specific module yet. I plan to confirm my group assignment and then learn more about the module I will be working on
Week of 19 October 2026
Instruction Immediate Module
This week, I started working on the Instruction Immediate module (instr_imm.sv) for the processor core. I was assigned to the implementation issue and followed the team’s Git workflow by forking the main repository, creating a feature branch, and working on the module there.
Before writing the module, I learned how the different RISC-V immediate formats work. I learned how to reconstruct I-type, S-type, B-type, U-type, and J-type immediates from different parts of the 32-bit instruction. I also learned how sign extension works and why branch and jump immediates have a zero as their least significant bit.
For the implementation, I used the opcode to determine the instruction type and funct3 to handle the special shift-immediate instructions. The module now generates the 32-bit immediate for the supported instruction types.
I used Verilator to check the module for syntax and lint errors, and it passed without warnings or errors. I then committed the changes, pushed them to my feature branch, and opened a pull request. The pull request is currently waiting for code-owner review.
I am still getting used to remembering the exact bit positions for each immediate format, especially B-type and J-type, but I understand the general process much better now. I have not started the Level 1 testbench yet because that will be part of next week’s verification work.