Xingyu’s Design Notebook
Week of 14 September 2026
Project Work
- First Design Notebook PR #560: Created my first design notebook and submitted a pull request.
This week, I set up my development environment by configuring Git, GitHub, and SSH authentication. I forked and cloned the official repository, created a working branch named xingyu-lab1, and added my first design notebook. I committed and pushed my changes to GitHub and opened PR #560.
During the setup, I initially entered the cd command incorrectly because I missed a space. I corrected the command and successfully navigated to the repository. I also verified that SSH authentication and Verilator were working correctly.
Lab 1: My First RTL Project
- My Onboarding Repository: Completed Lab 1.
I am not familiar with Git and SystemVerilog yet. For this lab, I mostly copied and pasted the example code from the lab manual. I created a simple AND gate and a testbench. I followed the instructions to use Verilator, and all four tests passed.
I learned some basic Git commands and how to run a simulation. I still don’t fully understand all the SystemVerilog code, especially the testbench. I also had some trouble using Terminal because I accidentally typed file names as commands. I hope to understand the code better in future labs.
Week of 27 September 2026
Lab 2: SystemVerilog RTL Fundamentals
This week, I completed Lab 2 and learned the basics of SystemVerilog RTL. I built an ALU using always_comb, a counter using always_ff, and a Moore FSM that detects 1011. I also learned the difference between blocking (=) and nonblocking (<=) assignments.
For most of this lab, I followed the lab instructions and copied and pasted much of the provided code, then modified the missing parts and ran the tests.
I had some trouble saving alu.sv in Pico because of an “Illegal byte sequence” error. I solved it by writing the file from Terminal using cat and EOF. I also had trouble understanding overlapping FSM transitions, but I learned that the FSM keeps partial matches instead of always returning to S0.
All ALU, counter, and sequence detector tests passed with Verilator.