Week 0
I set up my dev environment and reviewed some systemverilog stuff. I also reviewed the RV32I spec.
I’d like to work on the core, but I’m happy to help out with any area of the project.
Week 1
I spent this week looking back over Patterson and Hennessy book. I mostly focused on the high-level designs and diagrams of the datapath and control unit.
I found it nice how simple the overall design is compared to some more complex digital designs I’ve worked on, where the microarchitecture can look very different from the execution model. In particular, it was useful to review how the instruction format and control signals map fairly directly onto the components of a simple single-cycle processor.