Week 1
I set up my dev environment and reviewed some systemverilog stuff. I also reviewed the RV32I spec.
I’d like to work on the core, but I’m happy to help out with any area of the project.
Week 2
I spent this week looking back over Patterson and Hennessy book. I mostly focused on the high-level designs and diagrams of the datapath and control unit.
I found it nice how simple the overall design is compared to some more complex digital designs I’ve worked on, where the microarchitecture can look very different from the execution model. In particular, it was useful to review how the instruction format and control signals map fairly directly onto the components of a simple single-cycle processor.
Week 3
I planned out support for B-Type conditional branches and added the block diagram to miro. The basic idea is that we use the ALU to do the comparison (using either SUB, SLT, or SLTU). We can then use the ALU outputs (zero flag + result) and the value of funct3 to decide whether to take the computed branch target, or pc + 4. To compute the branch target, we need to decode and sign-extend the B-type immediate (which i also wrote out the logic for).
Week 4
Attended the weekly VIP meeting, where we discussed the processor design. Talked about the branch decode module; implementation, how to share logic with other modules, etc.
Week 5
Attended weekly meeting and got assigned to branch decoder module. Started to plan out the module. Trying to familiarize myself with best practices for systemverilog development and verification.