Ray Wang’s Design Notebook
Week 1
This week I completed Lab 1. I installed Git and Verilator with Homebrew on macOS, created a public onboarding repository, wrote a two-input AND gate in SystemVerilog plus a testbench, and ran the simulation with Verilator until all four cases passed. I also went through the full GitHub workflow: branch, commit, push, open a pull request, and squash-merge into main.
I learned how Verilator turns SystemVerilog into a runnable simulation, and why generated files like obj_dir/ belong in .gitignore. The logic type and the testbench #1 delays still feel new, but the AND-gate example made the basic RTL-plus-testbench flow clearer.
The main problem was GitHub setup. I first created the repositories on the wrong account, then had to move everything to zw4892-ray. I finished authentication in Safari and added a separate SSH key for this account.
I am especially interested in Bus/SoC and UART+SPI, and I hope to spend more time learning these areas this semester.
Work
Week 2
I read two pieces on how a processor runs instructions. In Patterson and Hennessy Chapter 4, I traced a single-cycle MIPS datapath for lw, sw, add, sub, AND, OR, slt, beq, and jump. The clock has to fit the slowest path, which wastes time, so pipelining overlaps instructions. Epstein’s E20 manual is the 16-bit CPU I am building: $0 stays zero, memory has 8192 words, and the same code runs on single-cycle, multicycle, or pipelined hardware with forwarding and stalls.
Week 3
I traced the S-type store path on the single-cycle datapath.
The S-type store path handles sb, sh, and sw. Opcode 0100011 selects it. A 12-bit immediate is assembled from instr[31:25] and instr[11:7], then sign-extended to 32 bits so a negative offset stays negative. ALUSrc selects this immediate instead of rs2, and the ALU adds it to rs1 to form the address. The rs2 value bypasses the ALU and is written to memory. MemWrite is 1 and RegWrite is 0, because a store does not write a register. funct3 selects an 8-, 16-, or 32-bit write. A separate adder computes PC + 4, since the ALU is already busy with the address.
Week 4
I read the MICRO-ARCHITECTURE documents: the module spec, the Sep 22 brainstorm, the schema credits and control table, the schema drawing, and the RV32I instruction card.
Last week’s meeting split the single-cycle datapath by instruction format. My part was the S-type store path, which is already in Week 3. Comparing that note with the written schema, three things do not agree.
The credits document steps the PC by 2 and saves PC+2 as the JAL and JALR link address, because instruction memory is halfword-addressable. A normal RV32I toolchain expects a byte address and PC+4. Tony’s note instead treats the PC as a byte address that advances by 4 and needs 15 bits, while the module spec still says only the low 14 bits are used. A 14-bit halfword index with a step of 2 covers all 16,384 instruction-memory locations. A byte address needs a step of 4 and 15 bits. Week 3 followed the textbook and used PC+4, so that line has to change if the group keeps PC+2.
The LBU example sets read_size to 1 and calls it a byte load. In the same table, 0 is a byte, 1 is a halfword, and 2 is a word, so that example should be 0. AUIPC is also added in two places: the credits document sends the PC into the ALU, while Tony says the existing branch adder already computes PC plus an immediate.
Work
- Reviewed the MICRO-ARCHITECTURE documents and compared them with the S-type store path from last week’s meeting.
Week 5
I received the design assignment, learned about the work content for the next two weeks, connected with and discussed the next steps with my team members, and understood the requirements for the three-level verification.