Ray Wang’s Design Notebook
Week 1
This week I completed Lab 1. I installed Git and Verilator with Homebrew on macOS, created a public onboarding repository, wrote a two-input AND gate in SystemVerilog plus a testbench, and ran the simulation with Verilator until all four cases passed. I also went through the full GitHub workflow: branch, commit, push, open a pull request, and squash-merge into main.
I learned how Verilator turns SystemVerilog into a runnable simulation, and why generated files like obj_dir/ belong in .gitignore. The logic type and the testbench #1 delays still feel new, but the AND-gate example made the basic RTL-plus-testbench flow clearer.
The main problem was GitHub setup. I first created the repositories on the wrong account, then had to move everything to zw4892-ray. I finished authentication in Safari and added a separate SSH key for this account.
I am especially interested in Bus/SoC and UART+SPI, and I hope to spend more time learning these areas this semester.
Work
Week 2
I read two pieces on how a processor runs instructions. In Patterson and Hennessy Chapter 4, I traced a single-cycle MIPS datapath for lw, sw, add, sub, AND, OR, slt, beq, and jump. The clock has to fit the slowest path, which wastes time, so pipelining overlaps instructions. Epstein’s E20 manual is the 16-bit CPU I am building: $0 stays zero, memory has 8192 words, and the same code runs on single-cycle, multicycle, or pipelined hardware with forwarding and stalls.