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Design Notebook - SS20513

Week 1 - 09/21/26

Project Work

This week I reviewed basic SystemVerilog and computer architecture concepts and started reading the RV32I base integer instruction set documentation.

I also worked through the relevant parts of Lab 1 to become more familiar with the team’s Git/GitHub workflow. As part of the SystemVerilog exercise, I implemented a simple two-input AND gate and used a testbench to test the four possible input combinations.

What I Learned

From reviewing RV32I, I learned that RV32I is a 32-bit base integer instruction set with 32 integer registers, with x0 hardwired to zero. I reviewed the R, I, S, B, U, and J instruction formats and started learning how fields such as opcode, rd, rs1, rs2, funct3, and funct7 are used during instruction decoding.

The SystemVerilog exercise also helped me understand the basic relationship between a hardware module and its testbench. I used logic signals for the inputs and output and a continuous assign statement to implement the combinational AND operation. The testbench applies different input values and checks whether the output is correct.

I am also becoming more familiar with the GitHub workflow, including repositories, branches, commits, forks, and pull requests.

Preferred Project Areas

My first preferred area is the Single-cycle Core. I would like to learn how RV32I instructions are translated into hardware and how components such as the instruction decoder, ALU, register file, program counter, and control logic work together.

My second preferred area is Bus/SoC. I am interested in learning how the processor communicates with memory and memory-mapped peripherals.

Things I Would Like to Learn More About

  1. RV32I instruction decoding and ALU/control logic implementation in SystemVerilog.
  2. How the CPU communicates with memory and peripherals through the bus/SoC.

Challenges / Questions

Since Git and GitHub are relatively new to me, I am still getting familiar with the workflow of creating branches, committing changes, pushing them, and opening pull requests. I would also like to develop a better understanding of how the RV32I ISA maps onto a complete processor datapath.

Week 2 - 09/28/26

Project Work

This week I attended the second team meeting and continued learning about the architecture of the RV32I single-cycle processor. Our Group B task for the next two weeks is to create a microarchitecture diagram of the processor and document which features and instructions are supported.

I reviewed the main components that will need to appear in the processor diagram, including the program counter, instruction memory, register file, immediate generator, ALU, data memory, control unit, and multiplexers.

What I Learned

I learned that the datapath consists of the hardware components responsible for storing, moving, and operating on data. For example, the register file stores values, the ALU performs arithmetic and logical operations, and multiplexers select which values should be sent to different parts of the processor.

The control unit interprets the instruction and generates control signals that determine how the datapath should behave. Different RV32I instructions can reuse many of the same hardware components, with multiplexers and control signals selecting the appropriate data path for each instruction.

I also learned more about the role of the clock in a single-cycle processor. Combinational logic performs calculations during a cycle, while state elements such as the program counter and register file store values that are updated based on the clock.

Microarchitecture Diagram

I started identifying the major components and connections that should be represented in our RV32I microarchitecture diagram. My current understanding of the basic instruction flow is:

  1. The Program Counter (PC) provides the address of the current instruction.
  2. Instruction Memory returns the instruction at that address.
  3. The instruction is decoded by the Control Unit, and the source registers are read from the Register File.
  4. The Immediate Generator extracts and extends immediate values when required.
  5. Multiplexers select the appropriate operands for the ALU.
  6. The ALU performs arithmetic, logical, address-calculation, or comparison operations.
  7. Load and store instructions interact with Data Memory.
  8. A write-back multiplexer selects the value that is written to the destination register.
  9. The next PC is selected based on normal sequential execution, branches, or jumps.

Over the next week, I want to turn this understanding into a more complete microarchitecture diagram and connect the datapath components to the required control signals.

Supported RV32I Functionality

As part of the documentation, I am also working on identifying which RV32I instruction categories the processor needs to support. These include:

  • Integer arithmetic and logical operations
  • Immediate arithmetic and logical operations
  • Load and store instructions
  • Conditional branches
  • Jump instructions
  • Upper-immediate instructions

I still need to determine the exact individual instructions and any limitations that should be documented as supported by our implementation.

Next Steps

For the next week, I plan to:

  • Create the first complete version of the processor microarchitecture diagram.
  • Identify the datapath used by different RV32I instruction types.
  • Determine the major control signals required for the datapath.
  • Document the specific RV32I instructions/features supported by the processor.
  • Review the diagram against the RV32I documentation and the team’s processor requirements.