A Github repo of the RiSC-16 onboarding project was created and shared with Noah.
February 7th: Tim and I finished the two modules of Assignment 2 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code.
We implemented the instruction memory and program counter.
Flu-like viral infection restricted me and Tim from meeting at intended time.
February 10th and February 11th: Tim and I finished the two modules of Assignment 2 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code.
We implemented the arithmetic logic unit (ALU) and data memory.
Post-illness fatigue restricted me and [Tim] from finishing the assignment in one meeting, so we splitted into two meetings.
February 16th and February 18th: Tim and I finished the two modules of Assignment 3 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code.
We implemented the register file and control. We also ensured every positive clock edge write to the correct location in memory.
We were able to meet at the intended time; however, time constraints and conflicts necessitate to finish this in two separate meetings.
February 23rd: Tim and I finished the module of Assignment 4 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code.
We implemented the ALU testbench. We also wondered whether a dedicated folder should be created for testbenches.
Another module (Sixth RiSC-16 Module:
Control Module) of the onboarding project was included in the assignment slides, ofwhich not much information was shared. We henceforth decided not to accomplish it for now.