A Github repo of the RiSC-16 onboarding project was created and shared with Noah.
February 7th: Tim and I finished the two modules of Assignment 2 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code.
We implemented the instruction memory and program counter.
Flu-like viral infection restricted me and Tim from meeting at intended time.
February 10th and February 11th: Tim and I finished the two modules of Assignment 2 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code.
We implemented the arithmetic logic unit (ALU) and data memory.
Post-illness fatigue restricted me and [Tim] from finishing the assignment in one meeting, so we splitted into two meetings.
February 16th and February 18th: Tim and I finished the two modules of Assignment 3 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code.
We implemented the register file and control. We also ensured every positive clock edge write to the correct location in memory.
We were able to meet at the intended time; however, time constraints and conflicts necessitate to finish this in two separate meetings.
February 23rd: Tim and I finished the module of Assignment 4 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code.
We implemented the ALU testbench. We also wondered whether a dedicated folder should be created for testbenches.
Another module (Sixth RiSC-16 Module:
Control Module) of the onboarding project was included in the assignment slides, ofwhich not much information was shared. We henceforth decided not to accomplish it for now.
March 2nd: Tim and I started Assignment 5 of the onboarding project. However, we could not finish due to upcoming midterms so decided to proceed in the following week.
March 11th: Tim and I started Assignment 5 of the onboarding project. We successfully compiled and ran our RiSC-16 processor with the provided testbench and confirmed all outputs were corrects.
I implemented four SystemVerilog exercises: a 4-operation combinational ALU using a single assign statement, a 16-bit Fibonacci LFSR with XOR taps at bits 15, 13, 12, and 10, a composed module connecting two Mystery1 instances to a Mystery2, and a decoder/mux using an always_comb block.
I wrote C++ testbenches for four exercises: exhaustively verifying an ALU across all input combinations, sampling an LFSR across randomized initial values, randomly verifying a composed Mystery1/Mystery2 module, and testing a mux with don’t-care inputs by asserting output independence.
I added the NYU Processor Design registry and nyu-cmake/catch2 dependencies to the vcpkg configuration, structured the CMake build with an interface library and rtl/dv subdirectories, and converted all testbenches from bare main() functions to Catch2 TEST_CASE/REQUIRE blocks.
I read through advanced SystemVerilog material covering the logic/wire distinction, interfaces with modports for bundling inter-module port connections, and parameterized modules using #() syntax; no exercise was completed as the lab repository was incomplete.
Having forgotten to build the program for the Onboarding Lab 3, I built the program and pushed the updated lab into a forked GitHub repository.