Simon Hu - Design Notebook (Spring 2026)
Week 5
Comments:
Read the paper NYU Processor Design Team SoC CPU Core
Summary of the paper: This report introduces a single-core 32-bit CPU designed by the NYU Processor Design Team, supporting the RISC-V 32I instruction set. It employs a five-stage pipeline architecture (IF-ID-EX-MEM-WB) and implements key processor mechanisms such as branch prediction, a cache system, and hazard detection. The overall design is largely complete, with most modules implemented and tested, but further integration and verification are required to achieve a complete SoC tape-out.
Week 4
Comments:
Understand the core of verification. One output is from the Verilator, and the other is from the testbench.
Work done:
- revised the lab 3 and verified the testbench on exercise 2.
- terminal respond: simonlinux@DESKTOP-8L3L3I6:/mnt/e/NYU/processerVIP/onboarding-lab-3/build$ ./exercise2 Randomness seeded to: 2048508371 =============================================================================== All tests passed (404 assertions in 4 test cases)
Week 3
Comments:
Since in Lab 3 repo lack of header file, I first installed the verilator. Expected install in linux environment. Recommend learning Verilator: https://verilator.org/guide/latest/
Work done:
-
revised the lab 2 and verified the testbench.
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terminal respond: simonlinux@DESKTOP-8L3L3I6:/mnt/e/NYU/processerVIP/onboarding-lab-2/build$ ./dv/tests Randomness seeded to: 2918360953 =============================================================================== All tests passed (262654 assertions in 10 test cases)
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onboarding lab 2 link: https://github.com/1fHu/onboarding-lab-2.git
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finished onboarding lab 3
Core instructions:
cd build
cmake .. cmake –build . ./dv/tests
remember to add the testbench file to CMakeLists.txt e.g. add_executable(tests exercise1.cpp exercise2.cpp exercise3.cpp exercise4.cpp )
Week 2
Comments:
Busy week with conference travel.
Work done:
Still working on onboarding lab 3.
Week 1
Comments:
Onboarding Lab 1 and 2 is finished by last semester. Onboarding Lab 3 Repo is not ready for directly used; it needs more files, such as VExercise1.h, to run the testbench. The files are available to be found in onboarding lab 2 repo.
Work done:
Finished Onboarding Lab 3 Exercise 1 this week. Link to onboarding lab 3:https://github.com/1fHu/onboarding-lab-3