Aneesh’s Design Notebook
December 13th, 2023:
This will be my last entry for the semester; I will continue my research on the RISC-V architecture and how to integrate different components into our reimplmenetation; hopefully the RISC simulator will be done next semester so I can look into integrating the other components onto it.
December 8th, 2023:
I had a meeting with the main Core team - limited applicability to my specific work but useful to get a better understanding of the overall architecture.
November 29th, 2023:
Needed to scrap previous work since I know am working on the componentry that assists the simulator - in other words, continuing the research that I started on November 10th.
November 22nd, 2023:
Doing more research into the different componetry to be added to the simulator, still very WIP.
November 10th, 2023:
Looking into different componentry to be added - including “the memory model, input/output device models, ELF loader, etc” to work with the C++ Verilator models.
October 30th, 2023:
Currently waiting for RISC-V simulator to be developed - according to Vito Gamberini, “RISC-V32I is a fixed length instruction set with 47 instructions. It’s like 200 lines of code to write the CPU simulation in software. That’s the smallest part of this”.
October 23rd, 2023:
Project Work:
- Finished all labs
From here, I will now do research to see what I want to delve more deeply into; I’m leaning towards the simulators.
October 9th, 2023:
Project Work:
I fixed this branch such that the changes are made on a separate working branch. I’m almost done with lab 4 now which is good; I also talked in the Discord earlier today on how I would continue on the project after I finish the labs.
September 30th, 2023:
Project Work:
- Started Lab 3 here
I started working through the exercises and was making progress on the second part; however, I wasn’t sure how to use the testing framework properly with the second test so I stopped for now. I’ll try to make progress on the rest of this lab throughout this week
September 24th, 2023:
Project Work:
- Did Lab 2 here
I brushed up on some basic verilog and was able to build the project. I then worked on this weeks lab (sometimes peeking at the implementations done by Siddharth and Nicky if I got stuck) and was able to pass all test cases. Note that I plan on shifting my processor design work to be done on the weekend for the rest of the semester.
September 18th, 2023:
Project Work:
- Set up GitHub fork to work on projects and submit pull requests
- Did Lab 1 here
I got my GitHub repo set up and worked on setting up my development environment. I also got through the first lab. I plan on getting through the rest of them throughout this week.