Glad to be able to work directly on one of the subteams without having to finish these labs, since I think I would learn better by attempting work on the subteam.
Will look at the the nyu-mem repo for potential starting points or just a general where-abouts regarding this defunct subteam
Looked into one of the issues on nyu-mem about generating the ROM script using OpenRAM
The last commit regarding the ROM and RAM generation stated issues with the ROM Generation
Successful RAM generation
After reading at the docs available on OpenRAM, I have a slightly better understanding of what a potential config file could look like, but I still am not sure
Slight confusion on Rishyak’s comments on not tracking files generated by OpenRAM since on OpenRAM ROM Generation it states that after a successful generation there should be additional files such as
Its just a .py file, or a plain-text file that contains python code to be run directly
Has no association with outside classes as it is self sufficient, I might wrong regarding this statement, will come back to fix if is the case
Relooked at the open issue on nyu-mem regarding the Hex to Verilog python file
Am confused since this is labeled as module on Github, however can be as a script. so is the current file a module a script, or something in between
Also read up on the Onboarding Lab 4 regarding the Catch2 framework.
Unfortunately, due to my incompetence, I can not seem to figure out a feasible way to complete lab 3 just yet
The Catch2 Framework makes sense, adding the Verilog files that are to be tested, and then linking up the C++ test file and then running the tests that have been changed to work under the framework
I think even if a conference soon is not possible, working towards the process of being able to be funded for one would be very interesting and potentially increase membership if this is something we can get done relatively consistently. All this for more funding for the VIP so that we have the ability to do more
Read through Lab 5 regarding SystemVerilog. Seems quite interesting and I am unsure as to how much is needed for the mem-team since some system Verilog files get generated through OpenRAM already.
I may ‘borrow’ someones code to try working on Lab 4 as it seems learning how to write parts of the toolchain code which will be required for testing different areas of the NYU-Mem Subteam.
Will work on setting up environment, I already have Conda from a previous course at NYU, need to see what packages I need to install to start development.
Need to understand what the development process is here at this VIP
Relatively uneventful semester which was noted by the majority of the team members. Cameron suggested an overhaul for the VIP and most members were in
agreement including myself. Next semester will be interesting with us working through a rework and setting up a goal for the VIP that is attainable.
Hopefully with the classes I am taking next semester, I will be in a better position to be able to help out the team