Design notebook for James Jin (2024 Fall)
Oct. 7th - Oct. 13th, 2024
Work done
- Lab 5: read through lab 5
Working comments
In the past weeks I was fully committed to finishing a journal paper. Now that the urgent work is done, I have read the advanced system Verilog tutorial to understand some of the team’s rules with Verilog usage.
Oct. 14th - Oct. 20th, 2024
- Lab 5: further excercises
Working comments
I believe that I still need to brush up on my Verilog knowledge due to not taking further computer systems / hardware courses, so I decided to implement some of the examples shown in Lab 5. Reading the descriptions of concepts such as logic and wire gives me sufficient conceptual understanding, but I would be more comfortable with their usage through further exercises.
Oct. 21st - Oct. 27th, 2024
- Lab 5: practicing Verilog interface modules
Working comments
Lab 5 further introduces a new type of module, namely interfaces. I created an example interface to become more familiar with it, utilizing logic gates as the modports in the interface.
Oct. 28th - Nov. 3rd, 2024
- Lab 5: finished lab 5 by linking interface and submodules with top level module
Working comments
Finally to consolidate my understanding of more advanced Verilog concepts, I connected two logic gates using the interface previously defined.