Uma Nachiappan’s Design Notebook

A confused Doc Czar and her Processor Designing adventures…

Week of 23 January 2023

Project Work:

This week, I explored the tools on our Anubis IDE and started understanding more about how to use git and GitHub. I completed lab 1 from the onboarding series and learned about toolchains and CMake, and how to implement them to run simple programs.

I struggled a bit with linking my directories and files created in Anubis to my GitHub repository, but with a bit of Googling and with help from the VIP website guides, I was able to push my directory to GitHub and link it above.

I will be unable to complete Lab 2 next week, but I will work on both Lab 2 and 3 during Week 3 (Feb 5-12).

Week of 6 February 2023

Project Work:

I worked on Lab 2 and 3 this week with the intention to finish both by the weekend but alas, going to India for a week without internet means Lab 3 is a work-in-progress.

For Lab 2, I initially struggled with Exercise 2 until I searched up what a Fibonacci linear-feedback shift register was. After finding a diagram of how the component works, it was fairly simple to build the module. I needed a quick refresher on the always_comb statement, since I haven’t used it before. Overall, this lab was a good review/practice of Verilog after taking Digital Logic last semester.

In Lab 3, I completed Exercises 1 and 4, which were the ‘simpler’ multiplexers. I was a bit lost on how to start the code for the tests, but I took a look at the dv directory and module tests from Lab 2 as examples. I feel like my code is okay, and they work as desired, but there is likely a more efficient way to write those programs. If I get the chance/time, I want to take another look at my submissions for 1 + 4.

Next week, I want to finish off Lab 3, and try to complete Lab 4 – hopefully I’ll be able to catch up!

Week of 13 February 2023

Project Work:

Due to some personal issues, I am still behind on my partially-self-designated timeline. My progress on Lab 3 was on hold this week, but I’m determined to get Lab 3 and 4 completed next week.

I attempted to set up WSL on my laptop, but I ran into problems when I tried to install the additional packages (CMake, Verilator, etc). I tried to update Ubuntu, then install these packages, but it still wasn’t working for me. So, I decided to switch to setting up a virtual machine using VirtualBox instead. Fortunately, this worked out well, and I now have a functional Linux VM for future project work.

I also made a diagram/schematic for a Fibonacci LFSR for Lab 2 Exercise 2, and created a messy pull request to update the lab docs. This created a mess within my fork of the upstream repo, since I was trying to push from my main branch instead of creating a temporary branch for my changes. A huge shoutout to Rishyak who helped me clean up my fork and also taught me important info about Git and Github (including some very useful git commands).

Week of 20 February 2023

Project Work:

This week, I drafted a guide for working collaboratively that included pull requests, issues, teamwork, and working on team repos. I added a few sections about forks from Rishyak’s suggestions, but there are still a couple of questions/changes I’m probably going to make after I get some more feedback. I have found that I kind of enjoy writing documentation and guides, and I’m getting more used to markdown syntax LOL. I didn’t have much time this week due to the start of midterm season, so I’m still working on the labs and I unfortunately submitted this DN quite late.

Week of 27 February 2023

Project Work:

It’s been 84 years… but I finally finished Lab 3. I was procrastinating on Exercises 2 and 3 since I wasn’t sure where to start, but I took inspiration/clues from the tests of Exercises 2 and 3 from Lab 2, since the questions were similar. Mostly just relieved that this lab is completed and I can get going on Lab 4 next week before spring break. I feel a lot better about working on Lab 4 since it looks like some of the work is based off of Lab 3, which is now done.

I’m also learning the art of asking for what I want, so I am now appointed as Documentation Czar :) I wrote one guide and decided I wanted more, so here we are. I’ve started drafting a docs-ified version of Vito’s mini lecture on the structure of our future chip, but I don’t have a GitHub file yet since I’m trying to avoid a long gross commit history. I’m also going to meet with Vito next week to talk about the other roles & responsibilities of the Doc Czar.

Week of 6 March 2023

Project Work:

I managed to complete Lab 4 before spring break, but I am aware that there are probably a few issues - I still need to do some testing/debugging. It is not my best work for sure, but under my self-appointed time crunch I am glad it is completed and I can start thinking about what component I want to work on.

I also completed my first Doc Czar job - Rishyak asked me to take a look at the AMBA repo docs and check clarity and understanding. I made a PR for a couple of typos & other relatively small edits, but overall the docs were already well written.

Despite bringing my laptop with me during spring break, I did not get a chance to work on Vito’s lecture - but I have a clearer idea of what is needed after talking to Vito, so I want to get a good chunk of the draft this week.

Week of 20 March 2023

Coming back from break kicked my butt a little – so sadly did not get as much VIP work done this week as I would have liked. I read through Lab 5 for a better understanding of Verilog, then joined the Core team and implemented the PC module. I didn’t get a chance to write the tests before submitting this DN, but testing the PC should be fairly simple anyway - will hopefully be able to link the tests and a PR to my DN for next week.

I know I signed up to be Doc Czar, and I am still committed to the role - this was unfortunately a very weird week (personally and academically) so my documentation work was at a standstill from before break.

Week of 27 March 2023

I PRed a first version of the PC module and test, but Michael pointed out that I didn’t edit the CMake files, and I realized myself that my test program was written under sleep deprivation and therefore, was utter nonsense. I redid the test, edited the CMLs, and re-PRed… and success! The Verilator check passed and my module was merged.

Rielle has decided to join for me documentation, so we discussed the current docs to-do list, as well as what would happen in the future after significant module implementation. I also took charge of the docs issues in the core repo, namely a document explaining the development and testing process, and a folder that holds the outlines for un-implemented modules. As I was working on the first, I delegated the outlines to Rielle. I PRed a draft of the dev process doc, and Michael suggested a few edits that I can get done the upcoming week. After that, I want to claim another core module and get some work done on the still unfinished lecture.

Week of 3 April 2023

I added a “Best Practices” section to the Core docs I drafted last week, although I will probably add a few more tips as I think of them/they are suggested to me. Currently looking for any other docs issues and working on the lecture looming over my shoulder LOL.

I’m teaming up with Rielle for the end-of-semester presentation - we’re going to be discussing documentation and our similar learning curves regarding git and GitHub. I will also be contributing to Michael’s presentation about Core, since my official development work has been for this repo.

Very last minute before this DN, I claimed the CPU General Purpose Registers so I will be implementing these next week - now that I know how to properly test them.

Weeks of 10 and 17 April 2023

  • Core: Implemented General Purpose Registers module
  • Documentation: VSCode Extensions Compilation
  • Documentation: Memory Docs Check
  • End-of-Semester Presentation: Outlined Presentation

Big OOPS on my part, forgot last week’s design notebook.

I created the module for the registers that I claimed 2 weeks ago, and I outlined the verification tests that I have yet to write the full code for. Got caught up in midterms/finals :(

Got a request from Rishyak to compile some useful VSCode extensions that he has been using. I don’t have a proper commit for it yet but it is mostly done, I promise. Will hopefully PR in the next few days. Sean also asked me to check out some documentation for the Memory repo - looked good so far.

Rielle and I created an outline for what we wanted to discuss in our end-of-sem presentation and took charge of whichever topics we were most comfortable with.

I have a lot of loose ends to wrap up this week, but hopefully I can get everything done while not failing Algo.

Week of 24 April 2023

  • Core: Created Draft of Gen Regs Test
  • Documentation: PR’ed VSCode Extensions
  • Documentation: Core Docs to Wiki
  • End-of-Semester Presentation: complete! :)

Once again, I’m very late for the DN entries. My only excuse is finals season :(

I created verification tests for the general registers module, but I think I’m losing it because something was not working properly. It’s probably a tiny error that I missed because I wrote the test at… 2 am. Fixing it this week and will hopefully PR to core by the end of the week.

I PR’ed the VSCode extensions doc, but have not merged yet because I want to get the changes/edits done once and for all before the semester ends. If I don’t get to editing by Friday I will merge and make the changes later.

I transferred the Core Documentation to the repo Wiki per Michael’s request. Glad that Rielle and I could close out the Docs issues.

We finished the end of semester presentation! Relieved that a) it was on Zoom and b) it was not solo because I am a bundle of nerves

Still tying up loose ends and trying not to lose track of time… We shall see how the last few weeks go.