Thu’s Design Notebook

Hello, World! Welcome to my notebook.

Week of 11 September 2023

Project work:

This week was spent getting used to using Git on command line, learning and settting up virtual environments, installing the required tools for the labs, and completing onboarding lab 1.

I think the lab was a good introduction to toolchain. The document was very detailed and super helpful. I just learnt about CMake and Make during OS this same week so it was nice to get to chance to put some of my new knowledge to use!

Week of 2 October 2023

Project work:

Last week I was away on a conference so I didn’t get a chance to work on Lab 2. This week was spent reviewing Verilog, running the tests from Onboarding Lab 2.

I realize I’ve forgotten quite a bit (lot) of Verilog, but I’m now more confident after completing the lab. Next week, I’ll catch up on Lab 3+4.

Week of 9 October 2023

Project work:

Struggling a bit with the first few exercises, will review some concepts and finish the lab next week

Week of 16 October 2023

Project work:

Finished Lab 3. Took quite some time at first but after I got through the first 2 exercises the rest was straightforward. Felt a lot more comfortable with testing now.

Week of 23 October 2023

Project work:

Working on Lab 4. Have been pretty busy with work so will be updating the notebook a bit late…

Week of 30 October 2023

Project work:

Finished lab 4.

Week of 6-13 November 2023

Project work:

Read through Onboarding Lab 5 and blog post on SystemVerilog. Was super helpful, I realized there’s a lot about Verilog I didn’t know since I just naturally picked up on the language. No exercise for this lab.

Week of 20 November 2023

Finished the onboarding labs. Reached out to Michael to join core. I’ll be collaborating with Kyle to work on the outlines for the instruction cache and instruction cache manager. This week was spent mostly on reviewing module concepts from Comp Arch.

Week of 27 November 2023

Project work:

Started outlining the instruction cache manager. Worked with Kyle to figure out inputs, outputs, and registers for the manager.

Week of 4 December 2023

Project work:

Met with the core team to clarify a few features for instruction cache. For a prototype, this module should be sufficient. The instruction cache manager outline is basically done, will continue with L1 cache next week.

Week of 11 December 2023

Project work:

Finals week so a little busy but I’ll be making pull requests for the outline this weekend. Both are almost done, just need a little refining.