Week 1:

Onboarding went on pretty smoothly. Got a taste of the environment we’ll be using to design our processor.

Attempted and finished Lab 1. Got exposed to CMake Toolchain, and how CML works. While attempting the quests for Lab 1: make des not work on windows. Would not geenrate a makefile and thus used cmake –build . instead. When attempted to build on VsCode, ran into some minor issues with the header file missing directory even when specified in the CML using target_env_variables.

Also, Started reading up on using verilator.

Week 1 of February 2023 (week 2 lab)

Discussed the possiblities/alternatives for a new working environment for windows users since i’m struggling with the commands not indigenous to windows for CMake. After a great meeting on thursday, I plan on shifting to linux / Vs / Chocolatey / GnU for a better integration environment since CMake is the go to for us. Will take some advice from peers regarding the same. Opted to do writeups for the team on some verilog modules for the coming week. Shifting gears and starting the rest of the labs sooner.

Week 2 of February 2023 (week 3 lab)

I actually tried to ask chat GPT to make the verification for the modules discussed in week 3 of our lab. The results were very different and not how we coded our testbench, GPT made use of verilator commands and directly sourced the testbech from the command. Eager to know if we can use the same. Also, I might not be the best at testbenches and may have done some errors in this week’s lab. If i could have more sources for the same, it would be helpful.

Week 3 of February 2023 (week 3-4 lab)

Got too caught up in academics and job search. The VS Code environment set up as disucssed with vito and reverification of testbenches are going to be pulled early this upcoming week along with lab 4. Excited to start work on the actual design soon. Been practising my verilog concepts through my graduate course so be rest assured i’ll be upto the mark since I have been practising the same for Hack@DAC 2023.