already had the WSL on my laptop so installing the required softwares wasn’t a hassle.
had the github for long but never worked on team, so looking forward to it.
cmake was new for me, did take some time to install and get to know the stuff.
the answers for the exercise are in Readme.md files of the respective labs
had to look up LFSR, did some problems on it previously. Everything else is straight Forward brushing up basics.
completed the verification and encounterd a problem in exercise 2, rectified it.
starting on verification.
worked on lab3, not attaching the link yet
completed exercise 1,2 working on 3 and 4
in next week will complete the lab3 and maybe 4 too
researching on teams
brushed upon C++; working on lab4
researching on which to join after the onboarding labs.
encountered a build issue, cleared it
got to use some macros from catch2 dependecny
got hang of how all the packages work in the onboarding labs that we did
doing somemore work on them to get good hang of it.
planning on joining core team
don’t know the process but will text in the group.
completed the onboardingLabs
revised the RV32 from ComputerOrganization&Design textbook.
worked on some modules and tried to implement a singlecycledatapath version of rv32
completed the design of the moudles, excpet topModuleWrapper and testbenches
will contact the core czar and start work on the assigned work
got assigned to cache design
started working on it, after L1, will continue with others,
had the midterms couldn’t work on it good,
will complete this week
completed the L1_data_cache documentation.
implemented the L1_data_cache module upto write and read hits
misses should be implemeted
no specifications for tha cache were there, so chose typical
write back, with write allocate and write through cache
LRU replacement policy, only implemented in L1, brainstorming on how to do the L2
opened a PR, and micheal gave some suggestions,
going to work on them and inorder to test the module i have complete datapath
haven’t worked with heirarchy caches so looking for resources
Coded the typical version of a L1 cache,
tested the l1 module with a L2 simulation of different parameters
should look for better way to test this module
and also this was implemented using registers directly
for simulating representing this in regsiters is good enough but SRAMs should be preferred
once testing is done will implement the SRAM version
testing is successful for L1, tested for 2 types of various sets and LRU counter
need to implement ECC and improve the block size to reduce the miss rate
tested with the same L2 simulation module, need to improve that. looking for various options
implemented the SRAM version, testing will be completed in 3 days, after that i will PR it
and look for suggestions in the similar way i am coding L2 with 4 way
havent tested for miss rate and penatly, need to check them and use optimization techniques as per the req.
completed the testing for L1 Module, and started on L2
updated the documentation for overview and structural overview
made some changes to the module and tb for PR
as i was not comfortable in c++, i used sv for testing and after the testing is completed i started to convert it into c++, but i confirmed with michael and he’s fine with any testing as long its good.
Created Pull requests for all the work today and messaged micheal about this.
have 3 exams back to back so completely packed that why creating PR today.