Ben Feng 2024 Design notebook

week 3 of 19 September 2024

Project work:

I finished lab 1 this week and learned how to build new system with Cmake and also learned how to work in the virtual box for the first time.

The work enviorment was pretty struggling and especially how to getting used to with the Ubunto in the virtual box. Also, I done the pull request wrong and thankfully Vito help me out at the end.

week 4 of 26 September 2024

Project work:

There is a project for my electronics course and I spent most of my week on it. I just finished exercise 1 in the lab 2, and expecting to finish them next week.

week 5 of 3 October 2024

Project work:

I finished lab 2 this week, and review some basic verilog content like how to use clock to indicate when will the program start and how to assign output based on the what the input is.

The verilog grammar struggle me for a while since I haven’t touch it for the entire summer so I have to look up in the internet to check how to write the correct verilog code. Also, I spent some time with understanding what the question is asking for, and eventually I think I figure it out? Maybe.

week 6 of 11 October 2024

Project work:

Working on lab 3, and had some issues with the testing process. And dicussed with Vito, he said the VM is too old and helped me set up my WSL instead. Unfortunately the WSL also doesn’t work so Vito is trying to figure out the issue in WSL and hopefully it will work soon.

week 7 of 18 October 2024

Project work:

Dive into midterm study for this and next week entirely, going to continue to work on it after the midterm.

week 8 of 22 October 2024

Project work:

Still studing for midterm, going to resume to work on lab next week.

week 9 of 31 October 2024

Project work:

Restarted the lab with Vivado as WSL and virtualbox is not working for writing in system verilog and have to switch to Vivado and write in Verilog.

Spent quite a lot of time in figuring out how to diaplay the text in Vivado and how to write the testbench correctly and test all the possible values. Hopefully next week will finished exercise 3 and 4.

week 10 of 9 November 2024

Project work:

Finish lab 3 this weekend. All test run successfully in Vivado and the expected results matches the results in design file. exercise 3 is quite difficult as I don’t know how to call the function in the testbench file, so I re-written the design file in verilog so that it still follows the requirements and were able to tested it in the testbench. I still feel not very confidence with Verilog coding as every exercise in the lab 3 I need to learn something new from the internet (sometimes from gpt) to help me fix the issues in the code.