Week of September 11, 2023

Project Work:

  • Read up on GitHub functionality (mainly Repos, Branches, Forks, and Pull Requests)
  • Created first design notebook entry

Admittedly I won’t have much time this semester, so my goal is to at least complete the onboarding labs. I aim to start (and ideally complete) Onboarding Lab 1 by the end of next week.

Week of September 25, 2023

Project Work:

  • Started Onboarding Lab 1 in Anubis (don’t know how to link it yet)
  • I made my first CML file using Anubis, and got “Hello World” to print in the terminal.

I created a folder for my onboarding labs in my personal copy before realizing that wasn’t what I was supposed to do. Got slightly overwhelmed trying to figure out how to delete it - I feel like a toddler. Currently trying to find a good YT series to walk me through the baby steps of GitHub. Also still don’t how to directly link my work in Anubis to the Github repository, will ask Vito about it this Tuesday.\

For this upcoming week, I want to finish Onboarding Lab 1. This week, I didn’t make the stupid mistake of grading multiple homework problems so hopefully I’ll have time.

Week of October 2, 2023

Project Work:

I finally finished Onboarding Lab 1! I had to go to Rishyak and Vito’s office hours to wrap my head around GitHub, git, the whole shebang. I also downloaded VSCode which has improved my life significantly. Unfortunately I don’t think I’ll be able to start the next lab for a while since I’ll be super busy with dogsitting, midterms, and homework for Scientific Computing (T ^ T) . I’m hoping to get enough free time to finish Onboarding Lab 2 after my PDEs midterm on Oct 19th.

Week of October 9, 2023

Project Work:

  • N/A

I accidentally deleted this entry because I realized I hadn’t gone through all the steps to merge it with upstream, oopsies. Anyways I was too busy with dogsitting so I didn’t get any work done this week. Next week I’ll have a ton of midterms, so I don’t anticipate being able to complete much.

(Side note: while I was napping the dog I watching pulled my coat off a chair into his crate and was chewing on it. He completely wrecked my headphone dongle, but I couldn’t help but think it was a little cute.)

Week of October 16, 2023

Project Work:

In 1971, Intel 4004 was the first 4-bit microprocessor chip and released it as part of a package called MCS-4 (Micro Computing System - 4 bit). MCS-4 consisted of the following:

Intel 4004 Chip

  • (4001): 2048-bit ROM (256 8-bit instructions) with a 4-bit programmable I/O port
  • (4002): 4-registers x 20-locations x 4-bit RAM data memory (80 4-bit data words) with a 4-bit output port
  • (4003): 10-bit parallel output shift registers
  • (4004): 4-bit CPU chip

Staring at the diagram of Intel 4004 registers reminds me a lot of E15/E20 from Computer Architecture. That being said I have no idea what ths address call stack is, nor do I understand shift registers (and if they have any difference from the registers we cover in CompArch). For next week, I want to read up more on both of these things so I can better understand their significance to Processor Design.

Week of October 23, 2023

Project Work:

Notes on Flip-Flops:

Flip-flops are sequential logic devices; can use data from current and previous inputs/outputs. Terminology interchangable w/ “latch” (?)

SR Flip-Flop:

  • SR = “Set-Reset”, outputs are Q and ~Q.
  • SR Active-High: uses two NOR gates for implementation. Inputs generally low and considered “active” when inputs are high -> (think always @ posedge from Verilog) Once set == 1, Q is set to 1 until reset == 0.
  • SR Active-Low: uses two nand gates for implementation (reverse of Active-High).
  • Gated SR Flip-Flop: Two input and gates are added, with second inputs being enable. enable must be set for Q to be changed.

D-Type & JK Flip-Flops:

  • Have additional input pin for clock signal (clk), allows flip-flop to be triggered according to clock signal (think sequential circuit).
  • D-Type: Has data input, clk acts like enable pin for this.
    • If data signal goes high, then next clock cycle Q is set to 1 (vice versa for data signal going low).
    • set and reset now asynchronous -> can affect outputs Q and ~Q at any time. If both are active at the same time, flip-flop enters an invalid state -> outputs are unpredictable (BAD!)
  • JK:
    • J ~ set; K ~ reset.
    • 2-input and gates swapped with 3-input nand gates. Since third input of nand gate connected to opposing output, invalid state eliminated.

It was interesting to learn about how sequential circuits are implemented using flip-flops, which heavily rely on logic gates. Back in CompArch, logic gates were used to transition into Verilog, but felt kinda divorced from the subject as a whole. Seeing how circuits diagrams are thoroughly planned using logic gates was a really cool connection for me. I’m curious to see if the Core team has any circuit diagrams that use logic gates.

Week of October 30, 2023

Project Work:

  • Read about x86 call stack from Sruthi K’s “Cracking Assembly” series
  • Talked to Vito about call stack implementation in x86

The call stack is a data structure used to store . In x86, the ESP points to last item added on the stack, EBP. Removing addresses from the stack, through the ret or pop instructions, can imply that we are exiting a function call and are returning.

In terms of Processor Design, this doesn’t apply since it’s an OS topic. I think designating some registers to be used to possibly keep track of a call stack would be useful if we wanted our CPU to be capable of recursive or multiple nestings of function calls.

Week of November 6, 2023

Project Work:

Notes on Shift Registers:

Shift Register:

  • Sequential logic device that can store multi-bit inputs from one or more inputs, and transfer that data to one or more outputs.
  • Flip-Flops/Latches used to make stages; # of stages = # of bits
  • Like flip-flops, shift registers also have some memory: a stage’s output latch is connected to the next stage’s input latch. Each internal flip-flop connected to external clock pin (clk).
  • Flip-flops’ inputs only change outputs on next clock cycle (rising edge for active-high circuits). Value of bit stored in one flip-flop will shift to the next each clock cycle.
    • ex. In 4-bit shift register, takes four clock cycles to move single bit of data across all flip-flops

Modes of Shift Registers:

  • Data either output in parallel or series (getting flashbacks to EM lol).
    • Series: Bits are processed one-by-one; requires only one input/output.
    • Parallel: Multiple bits are processed simultaneously; requires multiple inputs/outputs for each bit.
  • Most chips are capable of 2 out of 4 modes:
    • Series in Parallel Out (SIPO) - One input, multiple outputs
    • Series in Series Out (SISO) - One input, one output
    • Parallel in Series Out (PISO) - Multiple inputs, one output
    • Parallel in Parallel Out (PIPO) - Multiple inputs, multiple outputs
  • While clk is often used as steady pulse (like metronome), for shift registers it is used like an enable pin -> Data gets selectively shifted from inputs to outputs
  • Most shift registers do left-to-right shifts (S0); Universal Shift registers have additional serial input so they can do right-to-left shifts (S1).
    • S0 == 1: DSR input enabled => any data input at DSR shifted left to right (serial).
    • S1 == 1: DSL input enabled => any data input at DSL shifted right to left (serial).
    • S0 & S1 == 1: D0, D1, D2, D3 inputs enabled => data shifted to corresponding outputs Q0, Q1, Q2, Q3 (parallel).

Some shift registers have two clock pins: one for the shift register and one for a storage register.

  • Shift-clock acts like traditional pulse, has enable for outputs (must be low for any output to be enabled) -> clk for inputs
  • Storage-clock acts like enable -> when storage-pulse is active, data is shifted in parallel to outputs -> clk for outputs

Even though I’m interested in software, I wanted to watch another video on the hardware implementation of chip design. I did this so I could further fill in the blanks between the early topics covered in CompArch. Also bit-shifts became one of my favorite topics this semester (after I spent nine hours grading homework problems for them lol), so it was cool to start getting an idea how they physically occur in the hardware. It was also cool to start seeing the connections to the single-cycle and multi-cycle implementations of E20. I wonder what the pros/cons of each mode are, and which ones are going to be implemented in the processor we’re building?

Week of November 13, 2023

Project Work:

  • N/A

Had a Stats midterm and needed to grade projects, so I wasn’t able to get any work done this week. Will try to attempt onboarding lab 2 over Thanksgiving.

Week of November 20, 2023

  • Reviewed methods to maintain Cache Coherancy (mainly bus snooping)
  • Researched all lingo used in “Thrashing the snoopy bus”
  • Read about False Sharing

I saw that the Core team was working on Caches and thought about a silly phrase Vito said in a previous recitation. I had heard of thrashing in the context of virtual memory back in CompArch (i.e. computer performance degrading due to frequent page swaps between physical memory and disk, which is meant to handle physical memory being overcommitted). I didn’t realize it could also apply to coherent (multiprocessor) caching as well.

After reading the wikipedia article on ‘False Sharing’, I thought would have been cool to take Distributive Systems with Jepst as my last CS elective,,, alas t’wasn’t meant to be.

Week of November 27, 2023

Project Work:

  • Read basics of RTL code in Processor Design
  • Skimmed the article for Verilator on Wikipedia
  • Played Rishyak’s infuriating Virtual Memory game

I had a lot of work to do coming back from Thanksgiving so I just read a couple of short articles. I tend to get psyched out by terminology/tools I haven’t seen before so I wanted to get myself used to before doing the labs. I imagine that the ProcDesign frequently uses Verilator to double check the logic written for a circuit in C++. I originally joined the team to work on software, so I imagine this will be a tool I see frequently in the future.

Week of December 4, 2023

Project Work:

  • N/A

I didn’t have any time this week because I had to actually study up on the x86 stack and also I was grading simcache projects. BTW students truly do suck at coding lmao ( T T)

Week of December 11, 2023

Project Work:

  • N/A

I won’t anything this week since I have a paper due this week and finals. If I’m still on the team next semester, I’ll try to finish all the onboarding labs ASAP.