Current Membership

Project Leadership:

Project leadership facilitate and administrate the academic aspect of the team, determine high-level objectives, and develop materials for a broad set of team requirements.

Faculty Advisor: Ratan Dey

Team Lead: Uma Nachiappan

Finance Manager: Rielle Lim

Czars:

Czars own their respective parts of the technology stack. They have complete discretion to make technical decisions, review change requests, set iteration goals, and develop materials directly related to their objectives.

CPU: Cameron Bedard, Xingzhi Dai

RISC-V core design

Memory:

Memory controller and bus design, and memory compiler integration

AMBA/Peripheral:

Everything AMBA-related, and essential peripherals

Simulator:

Verification simulator development and integration

Software:

RISC-V software and toolchain development

Onboarding/Documentation: Uma Nachiappan

Labs, project documentation, and outreach

Active Members:

Active members are currently enrolled with the team, or were enrolled in the most recent full semester. Each develops their own goals and works in conjunction with project leadership and czars to make sure those goals advance the project and develop valuable technical skills.

VIP

• Joshua Cho
• Ben Feng
• Ruichen Gao
• Darren Kuo
• Kyle Liu
• Noah Mays-Smith
• Xhovani Mali
• James Jin
• Anurag Tadapaneni
• James Xie
• Dmitri Lyalikov