Pingchuan’s Design Notebook

Hello! This is Pingchuan’s Notebook.

Week 1 (Sept. 18 - Sept.25)

Tasks:

Comments

This week, I installed vm for linux system, completed the cmake lab in the linux environment. Ran into a few issues during the building process, and mistook CML as commandline instead of CMakeLists. Pay more attention to commit message conventions. Starting to do lab 2 and will finish it by the end of week 2.

Week 2 (Sept.25 - Oct.2)

Tasks:

Comments

This week, I refreshed my memory on verilog, and got a bit confused about the different variable names, namely logic, reg, and wire. logic is often used to represent individual bits or signals in digital circuits, and it represents a single binary value that can be either 0 or 1. reg is a data type used to declare registers or storage elements in Verilog. Registers can store and retain values over time. wire is a data type used to represent a continuous signal or connection between logic gates or components. It carries values from one point in a circuit to another. Starting to do lab 3 and will finish soon.

Week 3 (Oct.2 - Oct.9)

Tasks:

  • Still finishing up lab.

Comments

This week, I was caught up in a busy work schedule, and was confused about writing verification codes. Aiming to finish lab 3 by the end of next week.

Week 4 (Oct.9 - Oct.16)

Tasks:

Comments

This week, I continued to work on verification codes. The idea of verification code is new to me so it took me some time to understand. Strategy of writing verification tests: implement the verilog modules as c++ functions first, then come up with a testing strategy to verify. For Don’t Care variables, the test needs to show that it really is irrelevant by testing an amount of possible values for it. Starting to do lab 4 and will finish soon, but may be a bit late because of the midterms.

Week 5 (Oct.17 - Oct.23)

Comments

  • Working on Lab 4, but caught up in midterms

Week 6 (Oct.24 - Oct.30)

Comments

  • Continuing to work on Lab 4.

Week 7 (Oct.31 - Nov.6)

Comments

  • Finished writing the verification codes for lab 4, but couldn’t get them to run.
  • After updating wsl and everything, read from the log that there were additional packs that it wants me to download; the verification codes worked eventually.

Week of Nov.6 - Nov.13

Tasks:

Comments

I was slow on the onboarding labs due to midterm preparations last week, and am destined to finish lab5/get started on actual work next week. This week, I learned more about verification using catch2 and nyu-cmake. I also learned about interface libraries, they are different from normal libraries in that they can consist of and files that aren’t compiled immediately.

Week of Nov.14 - Nov.21

Tasks:

  • Completed Onboarding Lab 5

Comments

This week I went through the tutorials in lab 5, learned about when to use wire, reg, and logic. Wire: for multiple driver circuits; logic: for single driver circuits(most things); reg: there are tricky restrictions, rarely used. Also learned how to use interfaces to simplify things when modifying interconnections between modules. After implementing the interface, we only need to modify the modports if we need to change the interconnections. Lastly, I learned about the #() syntax, with a parameter list inside. The list givea default values to corresponding parameters, which can be changed later.

Week of Nov.21 - Nov.27

Tasks:

  • Looked into the team descriptions and decided to work on AMBA. Reached out to Rishyak for instructions.

Week of Nov.28 - Dec.4

Tasks:

  • Still reading through the AMBA repo, got assigned the AHB decoder.

Week of Dec.5 - Dec.11

Tasks:

  • Talked to Rishyak about designing the AHB decoder.
  • Note: the decoder is meant to receive the address signal from the manager, and deliver the selX signal to the corresponding subordinate.
  • Wil read further into the AHB pdf.

Week of Dec.12 - Dec.18

Tasks:

  • This week I mainly focused on final exam preparation, so I will continue to design the AHB decoder next semester.

Summary of Fall Semester

  • Learned a lot from the onboarding labs, especially about writing verification codes, which was what created a lot of trouble for me.
  • Spend more time than I expected on the onboarding labs, and I am currently working on the AHB decoder.
  • I will find time to work on the decoder during the holiday, and hopefully have something done by the start of next semester.