Michael’s Spring 2023 Design Notebook

Week of January 23, 2023

Project Work:

This week was spent mostly on completing onboarding labs 1 and 2. I worked by myself to complete these onboarding labs. I also opened two issue reports about mistakes in the labs and they were resolved.

Both labs were a good post-break refresh on the basics of CMake, make, and Verilog.

Week of January 30, 2023

Project Work:

  • Onboarding Lab 3: Completed Lab 3.
  • Docs for Homebrew: Created documentation for using Homebrew on Mac to install the required dependencies for the onboarding labs.

This week was spent mostly on completing onboarding lab 3 with some time also spent on creating the Homebrew documentation. Overall, Lab 3 was very informative and helped me to better understand how to use C++ to test verilog modules.

For the Homebrew documentation, I had previous experience using Markdown but this was a good review and it was very helpful in understanding the structure of the website as I had to create a new section to add the documentation to (after trying to simply insert it into the lab section with poor results).

In the future, I want to add more explanations to the Homebrew guide about what the commands do as well as other useful features of Homebrew that may be relevant to this project.

Week of February 6, 2023

Project Work:

This week was spent mostly on completing onboarding lab 4. Lab 4 introduced a lot of new concepts and was very helpful in getting a better understanding of the toolchain we will be using. I did run into a few issues with CMake but Vito was able to help me out with the first issue and I resolved the other issues by switching from the GCC 12.2.0 kit to the Clang 14.0.0 kit.

I also took time this week to fix formatting errors and spelling mistakes in the onboarding documentation.

Week of February 13, 2023

Project Work:

  • ALU Design: Created, implemented, and tested a design for a RISC-V-32I ALU.

This week was spent learning more about the RISC-V-32I instruction set and then designing an ALU to work with the instruction set. I designed the ALU in Verilog and used our toolchain to test the design. After several iterations, it passed the tests I designed and so should be fully functional.

Week of February 20, 2023

This week was mostly spent further reading up on the RISC-V-32I instruction set and thinking about what to implement next for the core. I already plan to implement a sign extension module to be able to feed the 12-bit immediate values into the 32-bit ALU module as I had decided against including sign extension functionality in the ALU module for ease of testing and simplicity.

Week of February 27, 2023

Project Work:

  • Sign Extension Module: Created, implemented, and tested a design for a sign extension module for the 12-bit immediates.
  • Module Paramertization Plans: Made plans to update the existing core modules to use parametrization and other applicable concepts from Lab 5.
  • Core Design Project Plan: Created a project to organize and keep track of the progress of all the component modules that will make up the core.

This week was spent figuring out the future direction of the core design. I met with Vito to discuss the core and he provided me with some additional resources to look into for specifics on RISC-V core design. So far, we have decided to use a 5 stage pipeline design that people who took Computer Architecture should be familiar with.

We also discussed how to handle assigning modules to people to implement. To make it easier on people we plan to make outlines for the modules we need implemented so that when someone wants to implement a module they have a clear idea of what that module needs to do, what interfaces it uses, etc.

Week of March 6, 2023

Project Work:

This week was spent adding parameterization to the ALU and Sign Extension modules as well as organizing and creating issues for the core modules that will need to be implemented.

Week of March 20, 2023

Project Work:

This week was spent outlining various core modules so that people who want to start working on the core have specific and clear instructions for what each module needs to do and how it needs to do it. An outline for individual core modules that will interact with each other in the 5-stage pipeline was created and turned into a block diagram for the core.

Week of March 27, 2023

Project Work:

This week was spent outlining more modules and implementing the Branch Evaluation Module. I also started assigning module issues to members of the core team and reviewed pull requests from Uma for the program counter which eventually led to a fully functional program counter.

I also assigned some documentation issues as I want to get the documentation on how we create and test modules to the point where someone coming into the core team for the first time doesn’t have to go through the process of submitting a pull request only to be told they did not add their tests to the Cmake file or something similar.

I am very happy with where the core repo is as of now. However, there is still a lot of outlining work to be done and much of it is for the more complex modules like the general control and cache modules.

Week of April 3, 2023

This week was spent looking over and discussing the core repo documentation for the module functionality and development and testing process. This documentation should hopefully help onboard people quicker and make it easier for them to start implementing modules.

Week of April 10, 2023

This week was spent developing the IF/ID latch module. I created the module as well as tests to verify its functionality and was able to create a functional module. I did not get a chance to build the interface for the module yet but will do so once things like the CPU register module are completed so that I can test everything the IF/ID latch module interfaces with.

Week of April 17, 2023

  • Merged Documentation Pull Request: Helped Rielle update her branch to be able to merge with the main repo and merged her documentation pull request for additional module documentation.
  • Updated IF/ID Module Docs: Updated the IF/ID latch module documentation to match the functionality of the module. Also moved all the module and testing documentation into a single documentation folder with multiple subfolders and added hyperlinks to the module documentation to the readme.
  • Made module input and output names consistent: When through all the modules, tests, and documentation to ensure a consistent naming and style for the input and outputs of the modules.
  • Updated CPU Diagram: Updated the CPU block diagram with the updated input and output names for the modules.

The majority of this week was spent going through the existing modules, tests, and documentation to create consistent names for the various inputs and outputs. Every module was updated to ensure a consistent style of all lowercase for i/o names and then the tests, documentation, and CPU diagram were updated to reflect the new names. I then reorganized the documentation to put it all in a single folder; that folder then has two sub-folders, one for the development and testing documentation and one for the module documentation.

I also helped Rielle with her documentation pull request as there were initial conflicts that prevented merging the pull request with the main branch of the repo. Ultimately we were able to resolve the issue and successfully merge the request.

This week was also the first of what I hope to make weekly check-ins about team members’ assigned tasks. Currently. Uma is working on the CPU General Purpose Registers, Rielle is working on the Branch Address Calculator, and I’m working on the ID/EX Latch. Uma and Rielle are also both working on documentation for the repo which has been very helpful.

Week of April 24, 2023

Most of this week was spent working on the core presentation and fixing various mistakes in the CPU design I discovered in the process. The two big issues I found were that I had mixed up where the register and ALU outputs went for accessing memory and that I forgot to account for the different word sizes that can be used to read from or write to memory. They were relatively simple to fix but I spent a decent chunk of time doing it as I needed to update everything from the schematic, to the module outlines. It also didn’t help that I was in the middle of working on the presentation which involved a color-coded schematic where each pipeline was a different color. Fortunately, GIMP’s selection tools were easily repeatable and it saves the colors I used so my color-coded diagrams were easy enough to recreate.

The core presentation went well. It ran longer than I thought it would but I don’t think it was excessive and I covered everything I felt I needed to. I doubt it will be that helpful for onboarding future core team members but it was good for me to get all the design goals and accomplishments in a single place and to have a record of the design as it stands today for reference when questions about the design arise in the future.

As finals approach, I expect work on the core repo will slow down a bit. Fortunately, the progress made up to this point has been quite substantial, especially given our small team size. I’ve currently assigned myself the ID/EX latch module to implement but that will probably be on hold for a bit as I want to outline more modules in hopes of having easier onboarding next semester. For modules like the General Control Module, Hazard Detection, Processor State, Cache Managers, and Branch Predictor, I wonder how practical our current approach to outlining will be. These are far more complex modules so I want to spend time writing a high-level overview of their functionality that can hopefully later be translated into our standard outline. I already have a basic overview of how they will work in my head so I just need to translate that into writing that others can easily understand.

The modules I will probably need the most help with are the caches. I am familiar with how caches and caching work, but most of my intuition for things like the size and distribution of the caches is based on modern multicore 64-bit X86-84 and ARM-64 CPUs. I will need to get information from the memory team on the size and layout of the memory as well as the overall memory map so I know what addresses correspond to ROM vs RAM. Our caches will also all be SRAM based so I’ll need help from the memory team with creating those using openRAM. The physical layout of the core is also important for the caches, as L1 needs to be the closest to the core followed by L2 then L3 then RAM.

Week of May 1, 2023

The majority of time this week was spent working on outlines for modules, specifically for stuff like the cache managers and general control module. As I expected, things are slowing down as finals approach but we are still making good progress.