Design notebook for James Jin (2024 Spring)

Feb. 5th - Feb. 11th, 2024

Work done

  • [Design notebook task]: was granted access to the repository and opened a pull request for this update.

Working comments

I decided to join the processor design team after a discussion with professor Dey on my interest in a deeper understanding of computers’ mechanisms. Due to my existing committments in the CS undergraduate research course, I have decided to enroll in the VIP with zero credits to familiarize myself with the work. However, I am particularly interested in optimizations and will aim to applying my theoretical / higher-level programming knowledge. Of course, I remain open to learning new things about hardware.

Feb. 12th - Feb. 18th, 2024

Work done

  • Lab 1: completed the first lab using a WSL ubuntu distribution.

Working comments

For each of the future weeks, I aim to complete at least 1 lab. At least with this 1st lab, I found my existing familiarity with some specific cmake and build tool commands allowed straightforward completion of the labs. Nevertheless, I learned the concepts of build tool, toolchain, and cmake.

Feb. 19th - Feb. 25th, 2024

Work done

  • Lab 2: briefly begun lab 2

Working comments

Due to extra research duties, I couldn’t complete lab 2. Given next week’s paper deadline, lab 2 will likely be further delayed. Nevertheless, I intend to at least update my cmake installation to enable building the project. Thus, I aim to complete and test another exercise.

Feb. 26th - Mar. 3th, 2024

Work done

Working comments

Lab 2 is fully complete and tested. I found my memory of verilog syntax rusty, but my awareness of combinatorial vs. sequential logic is still strong. Critically, I learned the different implication of “`include” in verilog vs. in C++/C. I look forward to learning about writing tests in lab 3.

Mar. 4th - Mar. 10th, 2024

Work done

  • Lab 3: completed exercise 1 (out of 4) for lab 3

Working comments

After finishing the verilog code for the modules of lab 2, I am then tasked with writing C++ testcases for such verilog. I understood and implemented the basic strategy of iterating through all input combinations, simulate output, and verifying correctness.

Mar. 11th - Mar. 17th, 2024

Work done

  • Lab 3: completed exercise 2 for lab 3

Working comments

While applying similar testing strategies as the start of lab 3, I leveraged the given credibility of the existing module and only tested unique combinations of bits that affect the output. This significantly reduced the amount of test cases required.

Mar. 25th - Mar. 31st, 2024

Work done

  • Lab 3: begun exercise 3 for lab 3

Working comments

Exercise 3 of lab 3 is tricky due to the impossiblity of brute-force testing all possible inputs and the complexity of the module hierarchy. I decided to implement the mystery1 module as a separate function to more efficiently simulate its two identical copies in verilog.

Apr. 1st - Apr. 7th, 2024

Work done

  • Lab 3: completed exercise 3 for lab 3

Working comments

I successfully finished the test code for exercise 3 after adopting a random number generation strategy. This was feasible due to the modules only affecting bit positions instead of operating on bit values. I verified the correct behaviours of the complex hierarchy through repeated testing.

Apr. 8th - Apr. 14th, 2024

Work done

Working comments

For various factors such as conference paper deadline and internship search, the work done in the past month is limited to lab 3. My tasks until the semester’s end should be split between labs and instruction cache duties assigned by Michael.

Apr. 15th - Apr. 21st, 2024

Work done

Working comments

Lab 4 involved a relatively straightforward refactor of lab 3’s verification code using the established interfaces and macros of the processor design team and Catch2. Nevertheless, I learned the cmake commands and vcpkg configurations necessary to enable these libraries.

Apr. 22nd - Apr. 28th, 2024

Work done

Working comments

Using my prior understanding of caches and verfication knowledge from this semester, I started strategizing tests for the eventually completed L1 instruction cache module. I plan to at least test for correct storage of data and the cache’s performance gain over memory.