Sean Doyle Design Notebook

Welcome to my Spring 2023 design notebook.

Week of 23 January 2023

Project Work:

I completed the first lab this week which was all about using cmake and make files. The lab went pretty smoothly for the most part however I could not get cmake to make the Ninja build system files. When I tried running the commands in the tutorial cmake came back to me with errors because I did not have the following set:

CMAKE_MAKE_PROGRAM

CMAKE_C_COMPILER

CMAKE_CXX_COMPILER

I believe these are just settings within the cmakelist file that need to be set so if we need to use ninja in the future I’m going to have to look into that. I also did not realize I should put the lab in a git repo to link it here so I ended up doing the lab in its own separate directory and copying to a git repo afterwards and making one big commit. As a result the repo linked here does not really show a natural progression of my work but that’s just a first VIP notebook entry issue. Finally, I would normally set git to ignore the build directory but for the sake of showing I completed the lab I did not do this and included them in my commit. I’m not sure if this is the correct thing to do but it felt like it made sense. Overall the lab went pretty smoothly and I have a much better understanding of Cmake and make.

Week of 30 January 2023

Project Work:

I completed the second lab this week which was all about system Verilog and completing exercise related to it. The first exercise was not very hard, however I struggled with the second exercise. I had never used a Fibonacci Linear Feedback Shift Register before so I had to look online to see what it did. I started by following this site but I notices that the pseudo code in that website was putting bits into the output on the opposite end as what the test cases expected. I ended up looking at the test creation code to figure out the specifics of the algorithm (which bits corresponded to which taps and what end of the output to append the new bit) because I couldn’t get the pseudo code from the above website to pass the test cases.

I also struggled a little bit initially with exercise 3 because I thought I had to import the mystery modules on my own. I did not realize that they were automatically included until I looked at the cmake file so I spent a good 10 or 15 minutes trying all possible pathways I could think of to import the mystery modules. :laughing:

After finishing lab 2 I went back and took another look at Lab 1. Based on the discussion at our meeting this week I went to this site and installed ninja for my mac. After doing this I re-did the ninja section of Lab 1 and had no errors!

Week of 6 February 2023

Project Work:

I completed the third lab this week which was all about testing. It went pretty smoothly all things considered but I just ran into a bunch of small problems that made things take longer. None of these were very significant, they were were mostly me misunderstanding how the actual code was intended to work and as a result my tests did not verify the code’s function correctly. Also, for my exercise 4 tests I decided to test all possible inputs which takes about 30 seconds to do. If this were production code I would likely modify these tests to use randomness to pick a subset of inputs but I wanted to get a better feel for the limits of bruteforce testing all possible inputs.

This week, I also created a script that automatically built, made, and ran the tests within the toolchain because I got sick of typing cmake .., make, and then the test command over and over again. Additionally I started to work on some documentation for GitKraken which is the tool that I use to manage local git repos.

Week of 13 February 2023

Project Work:

I completed the fourth lab this week. It went pretty well however at the very end I tried compiling my code by running cmake and for some reason it compiled for ninja not for make. I went back through the original tutorial, double checked all of my work and then tried running cmake again, and it still compiled for the ninja build system. I cleared my build directory and recompiled and only then it created a make file. I’m not sure why this occurred but it was pretty confusing for a bit. Other than this minor hiccup the lab was pretty self-explanatory and went well.

Week of 20 February 2023

Project Work:

This week I began looking at the Risc-V documentation [here] (https://riscv.org), [here] (https://www.cs.sfu.ca/~ashriram/Courses/CS295/assets/notebooks/RISCV/RISCV_CARD.pdf), and in the spec manual. Most of it I do not understand yet but mostly I was hoping to get acquainted with the resources that way when I do have questions in the future I know where to look for answers. I found that the core instructions link that I referenced above to be the most helpful as that gave me a good idea of all the functionality that we will have to implement.

I also continued working on the GitKraken documentation that I started a few weeks ago. I added sections on committing, pushing, pulling, merging, switching branches, and creating new branches so it is pretty close to ready. I think I will add a few more pictures and then beta test it on someone before putting in a PR. Not sure when this will be because I don’t think this documentation is high priority but if I have some down time in the next few weeks it could be pretty soon.

Week of 27 February 2023

Project Work:

This week I completed the fifth onboarding lab which was all about advanced System Verilog syntax. It made sense overall and I liked learning about interfaces and how they can be used to explicitly link Verilog components together. I didn’t quite understand the difference between nets and variables because this section of the lab felt pretty technical and kind of flew over my head. It might have helped to see some examples so I might look up example code and add it to the lab to help others that struggled with this section too.

Week of 6 March 2023

Project Work:

This week I created the NYU-Mem repository. After talking with Vito I created the issues for the following tasks:

  • Mapping out the interface between the memory controller and the HPB
  • Implementing the memory control unit
  • Creating a decoder for ROM/RAM
  • Translating Hex to Verilog for ROM storage.

I then hopped on a call with Rishyak and Kevin and we looked over a PR that Rishyak had created for the mem repository that had an interface between the memory controller and HPB mapped out based on chats we had been having throughout the week. We deciding on adding a response flag but other than that kept what Rishyak had coded up.

Week of 13 March 2023

– Off for Spring Break –

Week of 20 March 2023

This week I worked on the memory controller in the NYU-mem repository. I worked with Vito on interfacing the NYU-mem repo with the Amba repo so that I could have access to the memory interface inside the controller. Also, I began researching more into OpenRAM and read this paper on the tool. I don’t fully understand how it works as I am kind of confused by the diagrams on the third page of the paper which show switching signals mid clock cycle to perform read and write operations, but I plan on digging more into this in the coming weeks as I imagine it will be pretty critical to implementing the memory controller device. I also cloned the OpenRAM repo and built the project, however, I cannot figure out how to run it to create any RAM designs. I’ve been a bit frustrated with the lack of documentation for OpenRAM and have yet to even find a good “Hello-World” OpenRAM tutorial for memory generation. Finally, I got Nicky started on implementing a hex to Verilog decoder that will be used later to implement the ROM on our processor.

Week of 27 March 2023

This week I started off by trying to implement the control signals outlined in this article on pages 15-16. I added the control signals and timing code to the memory controller module and implemented an OpenRAM interface that could interact with OpenRAM generated memory. I could not get the code to compile with the nyu-cmake functions so I reached out to Vito to see what I could modify to enable timing controls. After talking with Vito, he told me that it would be more beneficial to create a script to generate the OpenRAM memory that my code would interact with so I am going to redirect my efforts in the coming weeks to understanding how OpenRAM works and how to generate memory with it. I also improved the documentation in the NYU-mem repo. I tried to model the issues after the nyu-core issues and also added an issue for the OpenRAM memory generation code that I am working on now. I added a few new labels to the issues that I already have to provide more details on their status.

Week of 3 April 2023

This week I generated memory using the OpenRAM library for the first time. I followed this tutorial and created a simple configuration file for OpenRAM to run on. It took longer than expected to follow the tutorial because I installed OpenRAM in a different location than where they specified but after working out these details it generated memory perfectly fine. I then installed an application called Layout Editor in order to open the GDS file generated and got to see a visual representation of the memory generated. I also looked at the Verilog memory file generated and compared it to the sample one that Vito sent me. They looked very similar to one another which was good to see. I plan on learning more about the parameters that I can customize in the OpenRAM config file and documenting my steps to generate memory on this repo website in order to allow people in the future to re-create the memory I made.

Week of 10 April 2023

This week I continued to generate memory using the OpenRAM library trying out different parameters in the config file. I found this website which gave be a lot of useful information on what the parameters of the config file all do, and I changed the word_size and num_of_words to increase the amount of memory generated. The actual memory generation then took a lot longer than expected so it seems like OpenRAM is doing some pretty heavy calculations to create these large memories. I then tried to generate ROM and found limited success there. I started by setting the number of r/w ports to 0 and the number of read only ports to 1 because I thought that would generate memory that was only readable. This caused a bunch of errors to occur none of which I could solve. I ended up reaching out to the creator of OpenRAM halfway through the week and he told me that was the wrong way of generating ROM and he pointed me to the most recent release of OpenRAM which had a specific ROM generation script that I could run on some sample ROM config files. I updated OpenRAM and tried running the ROM generation script but still couldn’t get it to work. The ROM script relied on this technology called sky130 which I could not get installed based on the OpenRAM instructions found here I thought it might be an OS issue as all of the instructions and downloads are written for linux, so I reached out to Nicky halfway through the week to see if he could run the ROM compiler on his Linux VM. We still could not get it working by the end of the week so I asked Nicky to send an email to the OpenRAM creator as well just so that he knows a few people are experiencing the same issue. I also added an issue to the OpenRAM repo to add more ROM generation documentation because the OpenRAM creator asked me to do so in our email exchange.

Week of 17 April 2023

This week I worked primarily on documenting all the steps necessary to download OpenRAM and generate memory. I create an instructions Markdown file and wrote down instructions for OpenRAM installation, RAM generation and ROM generation. I also added more information on the files that should be generated and some extra resources to learn more about OpenRAM. I sent this documentation to Krzysztof and Uma and they both liked it. I also cleaned up the repository and added various files to the .gitignore to keep the repository clean in the future.

Week of 24 April 2023

This week I finalized my parts of the end of semester presentation that Nicky and I gave and then practiced my presentation a few times. I focused mostly on how to generate RAM and walking my audience through that aspect of what I did, but I also included more information on the future scope of the memory team. On Thursday, Nicky and I presented our information and it went really well. To wrap up work this semester I plan on just getting more people to try out the OpenRAM instructions that I made and have them let me know what problems that they run into.

Week of 1 May 2023

This week was pretty lowkey from me with processor design VIP work. I went to the meeting on Thursday and listened to the presentations from Vito, Rishyak, and Kevin. I also sent out a few messages to people asking them to try out my instructions to generate RAM documentation and then followed my own instructions one more time from scratch to make sure they made sense.