Michael’s Fall 2023 Design Notebook

Week of September 11, 2023

Project Work:

This week was spent mostly working on the MEM/WB latch module as well as starting the detailed outline describing how the general control module will work. I also spent some time cleaning up the repository by fixing spelling mistakes, removing old assignments, and more so that it is ready for the new semester and new students. Overall, the Core repo is now in a place where new students can easily be on-boarded into Core and given a task to work on.

At this point all the outlines for the simpler modules are completed, which means I need to start finalizing the designs of things like the branch predictor, caches, and more. For very complex modules like the general control module, I plan to have more detailed descriptions of their functionality in addition to the standard outlines. As mentioned, I have started the one for the general control module and others will hopefully follow soon. I am also hoping this semester that one or two of the students on the Core team will have enough experience to be able to help me with design decisions and outlining; this is especially true regarding double-checking work and troubleshooting. As more of the core is completed, fixing bugs in module interaction or instruction execution will require someone with detailed knowledge of the overall design, and I’d like to be able to delegate bug fixing and troubleshooting to other people so that it doesn’t take up all my time and slow down our progress.

Week of September 18, 2023

Project Work:

  • Added More Instruction Decoding Detail to General Control Module Documentation: Added more specified output details to the different instruction types.
  • Merged Hazard Detection Module into General Control Module: Decided to merge the hazard detection module into the general control module to reduce redundant inputs and registers, since both modules would have had very similar inputs and internal registers. Started documenting the hazard detection functionality in the general control module functionality document.
  • Added NOP instruction description to General Control Module Documentation: Added the decoding steps for the NOP instruction that will be used to stall the pipeline to prevent data hazards.
  • Updated ID/EX Latch Docs: Updated the ID/EX Latch Documentation with the new a_sel line and new values for b_sel line to allow the Load Upper IMM and Add Upper IMM to PC instructions to work.
  • Fixed Branch Evaluator Docs: Fixed the way the ALU output for branch conditions 1 and 2 is evaluated. Instead of taking the full output, it is now bitwise ORed together to get either a 1 or 0.
  • Moved Branch Prediction to ID phase: Updated the Branch Address Calculator to output the predicted next program counter value so that it can be immediately fed back to the program counter, making branch prediction happen in the ID phase rather than the EX phase.
  • Updated CPU Block Diagram: Updated the CPU Block Diagram in the ReadMe to reflect the changes made to the general control module, merging the hazard detection module into the general control module, the new inputs for the branch address calculator module, the new a_sel line for the ID/EX latch, and the new pc_en line for the program counter.
  • Merged Uma’s General Purpose Register Module: Worked with Uma to remind her of the changes she needed to make to the register module and then merged her completed module and test into the core repo.

This week was primarily spent working on the documentation for the General Control Module. I added more specific output details to each instruction type as well as merged the hazard detection logic into the General Control Module. Most of the details for the instruction have now been added and what remains should be added shortly. In terms of the complete documentation for all functions of the General Control Module, I’d give a rough estimate that we are 40% complete, as while instruction decoding is almost fully documented, I have only just started on the data hazard detection portion of the documentation and have not yet started on handling branch prediction hazards, how the branch manager and control module will interact to deal with branching hazards and flushing the pipeline, or how to handle initialization of the core on startup.

While updating the Control Module Documentation, I discovered several oversights I made in the overall core design regarding the execution of specific instructions and branch prediction. To fix the instruction oversights, I added a few more control lines to select new parameters that would allow instructions such as Load Upper IMM to function properly. I also realized that if I moved branch prediction handling from the branch manager to the branch address calculator, we could save an entire clock cycle and predict in the ID phase rather than the EX phase.

Finding and fixing various oversights in the core design reinforced the idea that I need to find one or two knowledgeable Core Team members to meet with and give a detailed overview of the RISC-V ISA and current core design so that they can help make design decisions, help troubleshoot, and most importantly, double check my work so that mistakes are caught and correctly early on. Thankfully, we have a much larger team this semester so I am hopeful I’ll be able to find one or two students with enough initiative and aptitude to take on this responsibility.

Week of September 25, 2023

Project Work:

This week was spent on a variety of things, most of which were design documentation-related. I continued my work on the functionality documentation for the General Control Module, adding missing inputs and outputs and continuing to fill in the various instruction decode outputs. I also started work on the functionality documentation for the Branch Prediction Module as I now have most of the components surrounding it finalized so I can begin working on its functionality in more detail.

I also did some optimization to the MEM/WB latch’s wbs input. This input determines the source of the data written to the destination register and my initial numbering system proved to be inefficient when trying to decode the load instructions. While adding the General Control Module outputs for the load instructions, I realized that the func3 of the load instruction could directly correspond to the wbs, and so changed the wbs numbering scheme to be a direct 1-1 with the func3 numbering of the Load instructions, with the wbs number corresponding to the ALU, something not used by the load instructions, neatly corresponding to the unused load func3 value of 3.

The new members who joined this semester should hopefully start finishing their labs next week, meaning implementation of the already outlined modules and the needed interfaces should pick up. On-boarding people to Core should be relatively smooth as there is plenty of detailed implementation work they can go ahead and start.

Week of October 2, 2023

Project Work:

This week was another documentation-heavy one, with much of the focus being on adding outlines and issues for interfaces and higher-level modules used to connect the base modules, which I’m calling connection modules. Dedicated folders were added for interface outlines and connection module outlines respectively, and I made draft outline templates for both. With the groundwork for that documentation laid down, I’ve delegated the task of refining and finishing the outline templates to Uma, as she is the Doc Czar. Once the templates are complete, I can start filling out the information for individual interfaces and connection modules. I also created issues for various interfaces and connection modules and added them to the Core Design and Implementation project. There are still many interfaces and connection modules that need to be solidified and turned into issues, something I’m hoping the eventual new Core Team members will be able to help with.

I also continued my work this week on documenting the functionality of the various complex modules, with most of the work going into the Branch Prediction module. However, I did not get much done with it other than improving the general outline and finishing the current inputs and outputs as the interface and connection module documentation took up most of my time this week.

As it stands, we are still waiting for the new members to finish the onboarding labs. Hopefully, I can get some interfaces outlined for easy implementation, as many of the simpler core modules have already been implemented. There is still a lot of design work that needs to be done however, so I am hopeful that one or two students will be up to the challenge and be able to help work on things like the cache and various interfaces needed.

Week of October 9, 2023

Project Work:

  • Outlined ID Interface: Outlined the ID Interface which connects the IF/ID Latch module to the ID/EX Latch module.
  • Outlined MEM Interface: Outlined the MEM Interface which connects the EX/MEM Latch module to the MEM/WB Latch module.
  • Updated General Control Module Docs: Updated the Complex Functionality Document for the General Control Module with the output decode information for I Type 3 instructions and added a section for hazard detection logic.
  • Merged Uma’s EX Interface Outline: Merged Uma’s outline for the EX Interface connecting the ID/EX Latch and EX/MEM Latch modules.
  • Changed Documentation Folders Names: Changed the name of the documentation folders to align with the formatting used for the documentation files they contain.

This week was spent mostly working on outlines for interfaces. I’m trying to get some more ready-to-implement tasks ready for when new students join so there is plenty for them to work on. We were able to get the outlines for all the latch-to-latch interfaces done this week so that is a good start. I also continued the work on the complex functionality outline for the General Control Module which is making good progress. I’m hoping the new members are going to be ready to join teams soon as progress has been slow with just me, Uma, and Rielle working on Core, especially when Uma and Rielle also have documentation responsibilities.

Week of October 16, 2023

Project Work:

The majority of this week was spent creating and finishing outlines for various interfaces and replacing the Processor State Module with the Pipeline Reset Module. Most of the major ready-to-implement interfaces are now fully outlined and can be implemented, meaning there is plenty of work for new students to do once they are onboarded. I also finally decided what to do with the Processor State Module, opting to replace it with the Pipeline Reset Module which will handle forwarding the next program counter address to the program counter and handle flushing and resetting the pipeline.

Core Team onboarding finally started this week, with people finishing the labs. Surya was the first new member to be onboarded this semester and they expressed a desire to work on designing the caches. I’ve assigned Surya the task of designing the L1 cache and we will see how that goes. I also communicated with Charan who expressed a desire to join the Core Team after they finish the onboarding labs.

Week of October 23, 2023

Project Work:

Due to being in the midst of several midterm projects, I was not able to get a lot done this week. However, I did manage to make time to finish the Flush Bus interface outline and to help Rielle with her module testing. We now have quite a few modules and interfaces ready and waiting to be implemented which is good for when more people start to join the Core Team.

Speaking of people joining the Core Team, I did expect we would have more people finished with the labs and joining teams at this point in the semester. I have had two people reach out so far, which is good, but we are going to need a lot more people soon so we can start working away at implementation and the rest of the design work.

Week of October 30, 2023

Project Work:

The majority of this week was spent on finalizing the branch prediction module. I decided to go with a 2-bit branch predictor which required a few new inputs to be added to the module. Both the functionality description and the module outline are now completed for the branch predictor so it is ready to be implemented. While finalizing the branch predictor, I also made some changes to the Branch Manager and EX/MEM modules. Originally, the branch_taken signal was latched into the EX/MEM Latch and then passed to the Branch Manager in the MEM phase where combinational logic would control the flush signal. However, I realized I could instead pass the branch_taken signal directly into the Branch Manager in the EX phase and then use sequential logic for the flush signal rather than combinational to achieve the same result of flush being set in the MEM phase without the timing issues of the combinational approach. Rielle was also able to finish her work on the Branch Address Calculator which was good so I was able to merge that into the main repo.

Week of November 6, 2023

Project Work:

This week was mostly spent on implementing the ID/EX Latch and Branch Predictor modules as well as starting work on the Branch Manager module. After not touching implementation for several weeks in the hopes that easy implementation tasks would encourage new members to join the team and quickly get to work, it is clear that approach was unsuccessful and we’ll need to go full steam ahead with the 4 current members, hopefully soon to be 5, committed to Core Team work. In terms of implementation, Uma has started work on the EX and Source Register Data interfaces so those should hopefully be complete soon. Once we get several interfaces complete we’ll be able to tackle all the otherwise fully functional modules that still need to be interfaced and then test the functionality of several modules together. Surya has also continued work on the L1 Cache, completing the Verilog implementation and complex functionality description. Once Surya finishes the L1 Cache outline and tests that should be another module implemented.

At this point in the semester, I am quite concerned that I have only had 2 new students reach out to work on Core, one of which has yet to complete the labs. At this point in the semester, everyone should have finished the onboarding labs quite a while ago and be well integrated into a repo team to work on implementing and/or designing components. I’m going to make the best of the current situation as I have no other choice, but I’d like to find a way to get more of the new students engaged and joining teams.

Week of November 13, 2023

Project Work:

This week was spent on two main tasks, implementing the Branch Manager and Pipeline Reset modules, and finishing the functionality documentation and outline for the General Control Module. This week continues the work I started last week on moving through implementation tasks by implementing two more modules. With the Branch Manager and Pipeline Reset modules implemented, the only unimplemented base-level modules left are the General Control Module, which I finished the outline for this week so is ready to be implemented, the Data Cache modules, which Surya is working on, the Instruction Cache module, and the Cache Manager modules, which can’t be outlined or implemented until all the caches are finished. I would like to have all the base-level modules outlined and implemented by the end of the semester and that is certainly doable at this point.

This was also the week I also finally finished the functionality documentation and outline for the General Control Module. No one seemed to be interested in working on the hazard detection logic when I asked, and given it was really the only thing left incomplete with this module, I decided to just tackle it myself. Working on the hazard detection logic revealed some timing issues with how the General Control Module stored instructions in registers, namely that the IF_ins register through everything off by a clock cycle. As such, I removed the IF_ins register, using the ins input to determine the instruction in the IF stage instead. I also realized that I have duplicated the pc_en output by having it both in the instruction decoding outputs and the hazard-related outputs. This was easy to fix as I also realized that pc_en didn’t work as part of the decode signals anyway since having it always disabled by a NOP instruction would cause NOPs to freeze the pipeline, so it was entirely removed from the decoding outputs and left solely as a hazard related output.

I also asked Vito this week whether we needed to implement the privileged part of the RISC-V ISA, which thankfully we don’t meaning we don’t need to implement the CSR registers or instructions. My conversation with him also cleared up my confusion about how ecall and ebreak would work in the unprivileged version of the ISA in that we can just treat both as NOPs.

Week of November 20, 2023

Project Work:

Most of this week was spent on implementing various interface modules in Verilog. I also looked into how to test modules once their inputs are converted to interfaces and realized that we can’t have interfaced inputs in a Top Level Module so the relevant connection modules will need to be implemented before testing of interfaced modules can occur. I also added issues for various connection modules and finished the outline for the MEM connection module.

Week of November 27, 2023

Project Work:

A major decision was made this week to put the development of interfaces on hold until the CPU core is completed and fully functional. The interfaces are not required for full functionality and while they do provide a cleaner way of connecting modules together and make updating connections between modules easier, those benefits were overshadowed by the lackluster handling of interfaces by Verilator, making testing needlessly more complex, and by the mistake I made of designing the interfaces before the connection modules, which ended up making designing the connection modules way harder than it had to be. Once the CPU core is fully functional, the interfaces can be redesigned and reimplemented as they do provide benefits, but that implementation is better left till after the CPU core is working and we have time to spare.

Putting interface development on hold allowed me to come up with a general template for the connection modules, as I didn’t have to worry about how I would work around the existing interface designs that were often at odds with my preferred design for the connection modules. The connection modules as now split into 4 major categories: Caches, Pipeline Stages, Controls, and Top Level. The Cache Connection Modules are self-explanatory; there are two of them, Data Cache and Instruction Cache, with each containing the cache modules and cache manager module for their respective cache. As such, the CPU will now communicate with the cache manager and caches via these connection modules, rather than directly with the cache manager as was the case before. Combining the various cache modules like this should make testing the caches easier. The Pipeline Stage category is the largest, consisting of the connection modules for the IF, ID, EX, and MEM pipeline stages. Each stage’s connection module contains the starting latch module for that stage, e.g. IF/ID for ID, along with all non-control-related modules contained in that stage. Notably, the IF Connection Module does not contain any latch module since there is no preceding latch for the IF stage; there is also no connection module at all for the WB stage as its only relevant module is the CPU Registers Module which is already claimed by the ID stage, as such, the MEM/WB latch outputs are simply inputs to the ID Connection Module. The final two categories contain a single connection module each. The control category houses the Branching Control Connection Module which contains the Branch Manager, Branch Predictor, and Pipeline Rest modules, as they are not cleanly tied to a single pipeline stage and have many interconnections between each other. Finally, the Top Level category contains the aptly named Top Level connection module which connects all the connection modules together alongside the General Control Module.

I have also had a number of people reach out this week about joining the Core Team. Kyle and Thu have taken on the Instruction Cache which now means at least one person is working on the design and implementation for all yet-to-be designed and/or implemented lower-level modules. Xingzhi also reached out and he is currently deciding what task he wants to take on. With several people now new to the Core Team, I plan to hold a Core Team and Core design overview meeting sometime next week for those interested. While I would have liked to reach this point much earlier in the semester, I am relieved that people are finally started to join the Core Team in decent numbers.

Week of December 4, 2023

Project Work:

This week I finished the outlines for various connection modules and implemented the EX Connection Module. At this point, the only module that has yet to be outlined and is not currently assigned to someone to be outlined is the Top Level Connection Module. Since the Top Level Connection Module is essentially the final step, as it contains all other modules, it will likely remain unoutlined until more progress is made on the cache outlines. In terms of the caches, I spoke to Surya and he is making good progress on the data cache modules. We have decided to leave the L3 cache for later as it is more of a nice to have than anything and not necessary to get the Core functional. I also held a meeting this week for new members of the Core Team as many people were asking me similar questions so I wanted to address them all at once. I went over the organization of the Core repo and our development process as well as the design of the Core and how each component worked together.

Week of December 11, 2023

Project Work:

This week I started work on implementing the ID Connection Module. I was able to finish the initial verilog implementation of the module and start working on the tests. Given that this is the last week of classes, I also requested that Core Team members create PRs with their work, even if unfinished, so that I could review it. Given that next week is finals and the semester is over, this is likely the last weekly design notebook entry I’ll make until the spring semester starts in late January. I may make a few sporadic entries here and there over break, however.