Week of 10 February 2025
Project Work:
- Completed Creating Github account and design notebook.
This week was mostly spent on figuring out how to use git to upload files and other content to github.
I am struggling with environment setup. I might need to upgrade my OS system and other software to sucessfully setup the environment.
Week of 17 February 2025
Project Work:
- I went through a few labs on the website to test if my verilog environment works on my laptop.
This week was mostly spent on setting up verilog on my computer. My teammates and I discussed together to find a time to meet together.
Week of 24 February 2025
Project Work:
- I successfully set up the verilog environment on my laptop.
- I started to get familiar with the 16-bit chip project.
This week was mostly spent on figuring out opcodes and diagrams in the pdf files of project. In this way, our team can meet next week and split works each person. Then we could work on verilog code of this project.
Week of 03 March 2025
Project Work:
- I got the job to work on register file after group meeting. I started getting familiar with it.
This week was mostly spent on figuring out register file functionality of the chip.
Week of 10 March 2025
Project Work:
- I started working on verilog code of register file. It was unfinished since I have two midterms this week.
- I also found I misunderstood the register file, but the instructor help me make everything clear.
This week was spent on clearifying my misunderstanding about register file via meeting on Thursday and bulding a frame of verilog code.
Week of 17 March 2025
Project Work:
- I finished register file in verilog and updated it to our github link.
This week was spent on coding the resigter file. In my team, each person works on different part of the chip. Since I finished register file, I will decide what to work on till next team meeting.
Week of 31 March 2025
Project Work:
- As discussed by team, I plan to work on program counter of this chip.
This week was spent on understanding the funcionality of program counter. I have not started coding yet becuase I have one midterm this week.
Week of 7 April 2025
Project Work:
- I finished most of the functionality of program counter and uploaded them on our github link.
- I coded pc + 1, pc + immediate value functionality. However, it was difficult to understand how Jalr instruction works in the chip.
This week was spent on coding the program counter. I will discuss Jalr instruction with my team members and update my code next week.
Week of 14 April 2025
Project Work:
- I finished coding for program counter and uploaded them on our github link. I added the variable for Jalr instruction and added default case for switch statement, which is used to receive the bit value from MUXpc_sel.
This week was spent on fixing the code of the program counter. Last week, I did not successfully made a pull request to the github repo, but we fix it this week. Our team plan to discuss the next step of our project next week.
Week of 21 April 2025
Project Work:
- As discussed in meeting, I found a few issues in our current files. For me it is register file. My register file is lack of MUX_tgt and MUX_rf singals from control unit.
- I also tried to install EDA playground to test our code together, but my macbook had installation problems.
This week was spent on detecting issues in my current files.
Week of 28 April 2025
Project Work:
- I tried to compile our files together and met many problems. For example, ALU file did not implemnt BEQ instruction, so I told my teammate to fix that.
- I also tried to go one step further: I read pipeline document and found my PC file was lack of stall signal. It seems there are more work to do.
I was busy this week and did not have time to update my code. This week was the last meeting. We had regular meeting on Thursday and gave our instructor some feedback to this VIP team.