Design notebook for James Jin (2025 Spring)

Feb. 10th - Mar. 16th, 2025

Work done

(Awaiting assignment of tasks due to scheduling conflict and being unable to participate in weekly meetings)

Working comments

This semester due to TA responsabilities, I cannot attend the weekly meetings for the VIP and thus waited for separate communication from leadership about tasks for this semester. Now I have understood this semester’s focus being building a Verilog implementation of a simple processor known as RiSC.

Mar. 17th - Mar. 23rd, 2025

Work done

  • Reviewing RiSC specifications: understanding the instructions, registers, and memory of the processor.
  • Implementing RiSC’s program counter and registers in Verilog: in progress

Working comments

I have taken note of RiSC’s register layout and began drafting up two Verilog modules. So far I am following along the VIP’s outlines for these modules, which clarifies their inputs and outputs.

Mar. 24th - Mar. 30th, 2025

Work done

Working comments

I finished up the the implementation of the two RiSC modules started last week. Specifically with the reigster file, it’s important to keep the value of register 0 as 0. It was a good refresher for Verilog syntax.

Mar. 31st - Apr. 6th, 2025

Work done

Working comments

Using the VIP’s directions on the capacity of data and instruction memory, I implemented the mechanisms for reading from memory and writing to it in the case of data memory.

Apr. 7th - Apr. 13th, 2025

Work done

working comments

This week I built the arithmetic logic unit (ALU) of RiSC. I had to refer to documentation of how different instructions should be executed, and once I knew the purpose of different flags and the roles of the ALU, the arithmetic was quick to implement.

Apr. 14th - Apr. 20th, 2025

Work done

working comments

I implemented the control unit of RiSC based on the incomplete specifications in the miniproject documentation. Here, I defined constants for the various opcodes for the first time and will have to also use them in the top level module, which is the work to come.

Apr. 21st - Apr. 27th, 2025

Work done

  • RiSC Implementation: top level module started

working comments

I started outlining the top level module connecting all components of the RiSC processor using the style defined in the miniproject documentation. I think my design approach will at least use logic for the program counter and some inputs to modules that depend on previous outputs.

Apr. 28th - May. 4th, 2025

Work done

working comments

I defined all components of the RiSC processor in the top level module and all the input and output connections. The design uses logic to make the opcode, ALU inputs, and register file inputs assignable, as those components need to change based on the instruction.